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Searched refs:vuip (Results 1 – 24 of 24) sorted by relevance

/linux-6.1.9/arch/alpha/kernel/
Dcore_apecs.c48 #define vuip volatile unsigned int * macro
138 stat0 = *(vuip)APECS_IOC_DCSR; in conf_read()
139 *(vuip)APECS_IOC_DCSR = stat0; in conf_read()
145 haxr2 = *(vuip)APECS_IOC_HAXR2; in conf_read()
147 *(vuip)APECS_IOC_HAXR2 = haxr2 | 1; in conf_read()
159 asm volatile("ldl %0,%1; mb; mb" : "=r"(value) : "m"(*(vuip)addr) in conf_read()
180 stat0 = *(vuip)APECS_IOC_DCSR; in conf_read()
191 *(vuip)APECS_IOC_DCSR = stat0; in conf_read()
200 *(vuip)APECS_IOC_HAXR2 = haxr2 & ~1; in conf_read()
218 stat0 = *(vuip)APECS_IOC_DCSR; in conf_write()
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Dcore_mcpcia.c102 stat0 = *(vuip)MCPCIA_CAP_ERR(mid); in conf_read()
103 *(vuip)MCPCIA_CAP_ERR(mid) = stat0; in conf_read()
105 *(vuip)MCPCIA_CAP_ERR(mid); in conf_read()
116 value = *((vuip)addr); in conf_read()
147 stat0 = *(vuip)MCPCIA_CAP_ERR(mid); in conf_write()
148 *(vuip)MCPCIA_CAP_ERR(mid) = stat0; mb(); in conf_write()
149 *(vuip)MCPCIA_CAP_ERR(mid); in conf_write()
158 *((vuip)addr) = value; in conf_write()
161 *(vuip)MCPCIA_CAP_ERR(mid); /* read to force the write */ in conf_write()
249 *(vuip)MCPCIA_SG_TBIA(MCPCIA_HOSE2MID(hose->index)) = 0; in mcpcia_pci_tbi()
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Dsys_alcor.c41 *(vuip)GRU_INT_MASK = mask; in alcor_update_irq_hw()
63 *(vuip)GRU_INT_CLEAR = 1 << (d->irq - 16); mb(); in alcor_mask_and_ack_irq()
64 *(vuip)GRU_INT_CLEAR = 0; mb(); in alcor_mask_and_ack_irq()
73 *(vuip)GRU_INT_CLEAR = 0x80000000; mb(); in alcor_isa_mask_and_ack_irq()
74 *(vuip)GRU_INT_CLEAR = 0; mb(); in alcor_isa_mask_and_ack_irq()
91 pld = (*(vuip)GRU_INT_REQ) & GRU_INT_REQ_BITS; in alcor_device_interrupt()
116 *(vuip)GRU_INT_MASK = 0; mb(); /* all disabled */ in alcor_init_irq()
117 *(vuip)GRU_INT_EDGE = 0; mb(); /* all are level */ in alcor_init_irq()
118 *(vuip)GRU_INT_HILO = 0x80000000U; mb(); /* ISA only HI */ in alcor_init_irq()
119 *(vuip)GRU_INT_CLEAR = 0; mb(); /* all clear */ in alcor_init_irq()
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Dsys_rawhide.c49 *(vuip)MCPCIA_INT_MASK0(MCPCIA_HOSE2MID(hose)) = mask; in rawhide_update_irq_hw()
51 *(vuip)MCPCIA_INT_MASK0(MCPCIA_HOSE2MID(hose)); in rawhide_update_irq_hw()
121 *(vuip)MCPCIA_INT_REQ(MCPCIA_HOSE2MID(hose)) = mask1; in rawhide_mask_and_ack_irq()
177 *(vuip)MCPCIA_INT_MASK0(MCPCIA_HOSE2MID(h)) = mask; in rawhide_init_irq()
178 *(vuip)MCPCIA_INT_MASK1(MCPCIA_HOSE2MID(h)) = 0; in rawhide_init_irq()
Dcore_polaris.c101 *value = *(vuip)addr; in polaris_read_config()
131 *(vuip)addr = value; in polaris_write_config()
133 *(vuip)addr; in polaris_write_config()
Dcore_irongate.c120 *value = *(vuip)addr; in irongate_read_config()
149 *(vuip)addr = value; in irongate_write_config()
151 *(vuip)addr; in irongate_write_config()
Dcore_tsunami.c133 *value = *(vuip)addr; in tsunami_read_config()
162 *(vuip)addr = value; in tsunami_write_config()
164 *(vuip)addr; in tsunami_write_config()
Dirq_pyxis.c101 *(vuip) CIA_IACK_SC; in init_pyxis_irqs()
Dcore_marvel.c555 *value = *(vuip)addr; in marvel_read_config()
585 *(vuip)addr = value; in marvel_write_config()
587 *(vuip)addr; in marvel_write_config()
1038 vuip addr; in marvel_agp_info()
1044 addr = (vuip)build_conf_addr(h, 0, PCI_DEVFN(5, 0), 0); in marvel_agp_info()
Dcore_lca.c143 value = *(vuip)addr; in conf_read()
180 *(vuip)addr = value; in conf_write()
Dirq_i8259.c129 int j = *(vuip) IACK_SC; in isa_device_interrupt()
Dsys_ruffian.c95 *(vuip) PYXIS_RESET = 0x0000dead; in ruffian_kill_arch()
Dcore_wildfire.c399 *value = *(vuip)addr; in wildfire_read_config()
428 *(vuip)addr = value; in wildfire_write_config()
430 *(vuip)addr; in wildfire_write_config()
Dsys_miata.c253 *(vuip) PYXIS_RESET = 0x0000dead; in miata_kill_arch()
Dcore_t2.c205 value = *(vuip)addr; in conf_read()
257 *(vuip)addr = value; in conf_write()
Dcore_titan.c156 *value = *(vuip)addr; in titan_read_config()
185 *(vuip)addr = value; in titan_write_config()
187 *(vuip)addr; in titan_write_config()
Dproto.h10 #define vuip volatile unsigned int * macro
Dsetup.c1314 car = *(vuip) phys_to_virt (0x120000078UL); in determine_cpu_caches()
/linux-6.1.9/arch/alpha/include/asm/
Djensen.h100 #define vuip volatile unsigned int * macro
117 return 0xff & *(vuip)((addr << 9) + EISA_VL82C106); in jensen_local_inb()
122 *(vuip)((addr << 9) + EISA_VL82C106) = b; in jensen_local_outb()
138 *(vuip)((addr << 7) + EISA_IO + 0x00) = b * 0x01010101; in jensen_bus_outb()
184 return *(vuip) ((addr << 7) + EISA_IO + 0x60); in jensen_inl()
196 *(vuip) ((addr << 7) + EISA_IO + 0x20) = b * 0x00010001; in jensen_outw()
203 *(vuip) ((addr << 7) + EISA_IO + 0x60) = b; in jensen_outl()
247 return *(vuip) ((addr << 7) + EISA_MEM + 0x60); in jensen_readl()
258 r0 = *(vuip) (addr); in jensen_readq()
259 r1 = *(vuip) (addr + (4 << 7)); in jensen_readq()
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Dcore_t2.h362 #define vuip volatile unsigned int * macro
376 *(vuip) ((addr << 5) + T2_IO + 0x00) = w; in t2_outb()
391 *(vuip) ((addr << 5) + T2_IO + 0x08) = w; in t2_outw()
397 return *(vuip) ((addr << 5) + T2_IO + 0x18); in t2_inl()
402 *(vuip) ((addr << 5) + T2_IO + 0x18) = b; in t2_outl()
483 result = *(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x08); in t2_readw()
498 result = *(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x18); in t2_readl()
510 r0 = *(vuip)(work); in t2_readq()
511 r1 = *(vuip)(work + (4 << 5)); in t2_readq()
523 *(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x00) = w; in t2_writeb()
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Dcore_lca.h220 #define vuip volatile unsigned int __force * macro
266 *(vuip) ((addr << 5) + base_and_type) = w; in lca_iowrite8()
302 *(vuip) ((addr << 5) + base_and_type) = w; in lca_iowrite16()
310 return *(vuip)addr; in lca_ioread32()
318 *(vuip)addr = b; in lca_iowrite32()
359 #undef vuip
Dcore_mcpcia.h250 #define vuip volatile unsigned int __force * macro
292 *(vuip) ((addr << 5) + hose + 0x00) = w; in mcpcia_iowrite8()
316 *(vuip) ((addr << 5) + hose + 0x08) = w; in mcpcia_iowrite16()
326 return *(vuip)addr; in mcpcia_ioread32()
336 *(vuip)addr = b; in mcpcia_iowrite32()
385 #undef vuip
Dcore_cia.h342 #define vuip volatile unsigned int __force * macro
374 *(vuip) ((addr << 5) + base_and_type) = w; in cia_iowrite8()
404 *(vuip) ((addr << 5) + base_and_type) = w; in cia_iowrite16()
412 return *(vuip)addr; in cia_ioread32()
420 *(vuip)addr = b; in cia_iowrite32()
482 #undef vuip
Dcore_apecs.h375 #define vuip volatile unsigned int __force * macro
420 *(vuip) ((addr << 5) + base_and_type) = w; in apecs_iowrite8()
456 *(vuip) ((addr << 5) + base_and_type) = w; in apecs_iowrite16()
464 return *(vuip)addr; in apecs_ioread32()
472 *(vuip)addr = b; in apecs_iowrite32()
515 #undef vuip