| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dml/dcn301/ |
| D | dcn301_fpu.c | 292 static void calculate_wm_set_for_vlevel(int vlevel, in calculate_wm_set_for_vlevel() argument
301 ASSERT(vlevel < dml->soc.num_states); in calculate_wm_set_for_vlevel()
303 pipes[0].clks_cfg.voltage = vlevel; in calculate_wm_set_for_vlevel()
304 pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz; in calculate_wm_set_for_vlevel()
305 pipes[0].clks_cfg.socclk_mhz = dml->soc.clock_limits[vlevel].socclk_mhz; in calculate_wm_set_for_vlevel()
421 int vlevel, vlevel_max; in dcn301_calculate_wm_and_dlg_fp() local
433 vlevel = 0; in dcn301_calculate_wm_and_dlg_fp()
435 vlevel = vlevel_max; in dcn301_calculate_wm_and_dlg_fp()
436 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.d, in dcn301_calculate_wm_and_dlg_fp()
440 vlevel = min(max(vlevel_req, 2), vlevel_max); in dcn301_calculate_wm_and_dlg_fp()
[all …]
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| D | dcn32_fpu.c | 256 int vlevel) in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch() argument
267 dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, false); in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
269 if (vlevel < context->bw_ctx.dml.vba.soc.num_states && in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
270 vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] != dm_dram_clock_change_unsupported) in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
535 unsigned int vlevel = context->bw_ctx.dml.vba.VoltageLevel; in dcn32_set_phantom_stream_timing() local
536 …unsigned int dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcCo… in dcn32_set_phantom_stream_timing()
537 unsigned int socclk = context->bw_ctx.dml.vba.SOCCLKPerState[vlevel]; in dcn32_set_phantom_stream_timing()
562 pipes[0].clks_cfg.voltage = vlevel; in dcn32_set_phantom_stream_timing()
1012 int vlevel) in subvp_validate_static_schedulability() argument
1043 …} else if (vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_vblank_w_m… in subvp_validate_static_schedulability()
[all …]
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| D | dcn32_fpu.h | 64 int vlevel);
72 int vlevel);
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| D | dcn20_fpu.h | 43 int vlevel);
53 int vlevel,
71 int vlevel,
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| D | dcn20_fpu.c | 1004 int vlevel) in dcn20_calculate_dlg_params() argument
1024 context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] in dcn20_calculate_dlg_params()
1064 …context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel]… in dcn20_calculate_dlg_params()
1065 …context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel… in dcn20_calculate_dlg_params()
1071 …bool cstate_en = context->bw_ctx.dml.vba.PrefetchMode[vlevel][context->bw_ctx.dml.vba.maxMpcComb] … in dcn20_calculate_dlg_params()
1576 int vlevel, in dcn20_calculate_wm() argument
1588 …pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel][context->bw… in dcn20_calculate_wm()
1592 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx]; in dcn20_calculate_wm()
1601 …context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_from… in dcn20_calculate_wm()
1632 pipes[0].clks_cfg.voltage = vlevel; in dcn20_calculate_wm()
[all …]
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| D | dcn30_fpu.h | 50 int vlevel);
70 int vlevel);
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| D | dcn30_fpu.c | 381 int vlevel) in dcn30_fpu_calculate_wm_and_dlg() argument
385 double dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][maxMpcComb]; in dcn30_fpu_calculate_wm_and_dlg()
386 …bool pstate_en = context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] != dm_dram_clo… in dcn30_fpu_calculate_wm_and_dlg()
393 pipes[0].clks_cfg.voltage = vlevel; in dcn30_fpu_calculate_wm_and_dlg()
395 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz; in dcn30_fpu_calculate_wm_and_dlg()
402 if (vlevel == 0) { in dcn30_fpu_calculate_wm_and_dlg()
419 pipes[0].clks_cfg.voltage = vlevel; in dcn30_fpu_calculate_wm_and_dlg()
452 …if (context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] == … in dcn30_fpu_calculate_wm_and_dlg()
524 dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel); in dcn30_fpu_calculate_wm_and_dlg()
629 int vlevel) in dcn30_find_dummy_latency_index_for_fw_based_mclk_switch() argument
[all …]
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn30/ |
| D | dcn30_resource.h | 72 int vlevel);
105 display_e2e_pipe_params_st *pipes, int pipe_cnt, int vlevel);
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| D | dcn30_resource.c | 1651 int pipe_cnt, i, pipe_idx, vlevel; in dcn30_internal_validate_bw() local
1679 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); in dcn30_internal_validate_bw()
1681 if (vlevel < context->bw_ctx.dml.soc.num_states) in dcn30_internal_validate_bw()
1682 vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge); in dcn30_internal_validate_bw()
1684 if (fast_validate || vlevel == context->bw_ctx.dml.soc.num_states || in dcn30_internal_validate_bw()
1685 vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported) { in dcn30_internal_validate_bw()
1696 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); in dcn30_internal_validate_bw()
1697 if (vlevel < context->bw_ctx.dml.soc.num_states) { in dcn30_internal_validate_bw()
1700 vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge); in dcn30_internal_validate_bw()
1706 if (vlevel == context->bw_ctx.dml.soc.num_states) in dcn30_internal_validate_bw()
[all …]
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn20/ |
| D | dcn20_resource.c | 1828 int vlevel, in dcn20_validate_apply_pipe_split_flags() argument
1891 for (vlevel_split = vlevel; vlevel <= context->bw_ctx.dml.soc.num_states; vlevel++) in dcn20_validate_apply_pipe_split_flags()
1892 if (v->NoOfDPP[vlevel][0][pipe_idx] == 1 && in dcn20_validate_apply_pipe_split_flags()
1893 v->ModeSupport[vlevel][0]) in dcn20_validate_apply_pipe_split_flags()
1896 if (vlevel > context->bw_ctx.dml.soc.num_states) in dcn20_validate_apply_pipe_split_flags()
1897 vlevel = vlevel_split; in dcn20_validate_apply_pipe_split_flags()
1915 if (split4mpc || v->NoOfDPP[vlevel][max_mpc_comb][pipe_plane] == 4) in dcn20_validate_apply_pipe_split_flags()
1917 else if (force_split || v->NoOfDPP[vlevel][max_mpc_comb][pipe_plane] == 2) in dcn20_validate_apply_pipe_split_flags()
1931 v->ODMCombineEnablePerState[vlevel][pipe_plane] = dm_odm_combine_mode_2to1; in dcn20_validate_apply_pipe_split_flags()
1935 v->ODMCombineEnablePerState[vlevel][pipe_plane] = dm_odm_combine_mode_4to1; in dcn20_validate_apply_pipe_split_flags()
[all …]
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| D | dcn20_resource.h | 126 int vlevel,
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| D | dcn31_fpu.h | 44 int vlevel);
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| D | dcn31_fpu.c | 484 int vlevel) in dcn31_calculate_wm_and_dlg_fp() argument
487 double dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; in dcn31_calculate_wm_and_dlg_fp()
503 pipes[0].clks_cfg.voltage = vlevel; in dcn31_calculate_wm_and_dlg_fp()
505 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz; in dcn31_calculate_wm_and_dlg_fp()
549 dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel); in dcn31_calculate_wm_and_dlg_fp()
552 …context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] == dm_d… in dcn31_calculate_wm_and_dlg_fp()
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn31/ |
| D | dcn31_resource.h | 47 int vlevel);
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| D | dcn31_resource.c | 1729 int vlevel) in dcn31_calculate_wm_and_dlg() argument
1732 dcn31_calculate_wm_and_dlg_fp(dc, context, pipes, pipe_cnt, vlevel); in dcn31_calculate_wm_and_dlg()
1765 int vlevel = 0; in dcn31_validate_bandwidth() local
1773 out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate); in dcn31_validate_bandwidth()
1790 dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel); in dcn31_validate_bandwidth()
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn21/ |
| D | dcn21_resource.c | 818 int pipe_cnt, i, pipe_idx, vlevel; in dcn21_fast_validate_bw() local
843 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); in dcn21_fast_validate_bw()
845 if (vlevel > context->bw_ctx.dml.soc.num_states) { in dcn21_fast_validate_bw()
855 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); in dcn21_fast_validate_bw()
856 if (vlevel > context->bw_ctx.dml.soc.num_states) in dcn21_fast_validate_bw()
860 vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, NULL); in dcn21_fast_validate_bw()
919 …dcn20_fpu_adjust_dppclk(&context->bw_ctx.dml.vba, vlevel, context->bw_ctx.dml.vba.maxMpcComb, pipe… in dcn21_fast_validate_bw()
950 *vlevel_out = vlevel; in dcn21_fast_validate_bw()
|
| /linux-6.1.9/arch/arm64/kvm/ |
| D | arch_timer.c | 651 bool vlevel, plevel; in kvm_timer_should_notify_user() local
656 vlevel = sregs->device_irq_level & KVM_ARM_DEV_EL1_VTIMER; in kvm_timer_should_notify_user()
659 return kvm_timer_should_fire(vtimer) != vlevel || in kvm_timer_should_notify_user()
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/inc/ |
| D | core_types.h | 115 int vlevel);
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn32/ |
| D | dcn32_resource.c | 1805 int vlevel = 0; in dcn32_validate_bandwidth() local
1835 out = dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate); in dcn32_validate_bandwidth()
1854 dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel); in dcn32_validate_bandwidth()
1998 int vlevel) in dcn32_calculate_wm_and_dlg() argument
2001 dcn32_calculate_wm_and_dlg_fpu(dc, context, pipes, pipe_cnt, vlevel); in dcn32_calculate_wm_and_dlg()
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| D | dcn32_resource.h | 105 int vlevel);
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn301/ |
| D | dcn301_resource.c | 1391 int vlevel) in dcn301_calculate_wm_and_dlg() argument
1394 dcn301_calculate_wm_and_dlg_fp(dc, context, pipes, pipe_cnt, vlevel); in dcn301_calculate_wm_and_dlg()
|