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Searched refs:vdpu_write (Results 1 – 12 of 12) sorted by relevance

/linux-6.1.9/drivers/media/platform/verisilicon/
Dhantro_g1.c24 vdpu_write(vpu, 0, G1_REG_INTERRUPT); in hantro_g1_irq()
25 vdpu_write(vpu, G1_REG_CONFIG_DEC_CLK_GATE_E, G1_REG_CONFIG); in hantro_g1_irq()
36 vdpu_write(vpu, G1_REG_INTERRUPT_DEC_IRQ_DIS, G1_REG_INTERRUPT); in hantro_g1_reset()
37 vdpu_write(vpu, G1_REG_CONFIG_DEC_CLK_GATE_E, G1_REG_CONFIG); in hantro_g1_reset()
38 vdpu_write(vpu, 1, G1_REG_SOFT_RESET); in hantro_g1_reset()
Dhantro_g2.c23 vdpu_write(vpu, status, G2_REG_INTERRUPT); in hantro_g2_check_idle()
38 vdpu_write(vpu, 0, G2_REG_INTERRUPT); in hantro_g2_irq()
39 vdpu_write(vpu, G2_REG_CONFIG_DEC_CLK_GATE_E, G2_REG_CONFIG); in hantro_g2_irq()
Drockchip_vpu_hw.c308 vdpu_write(vpu, 0, VDPU_REG_INTERRUPT); in rockchip_vpu2_vdpu_irq()
309 vdpu_write(vpu, 0, VDPU_REG_AXI_CTRL); in rockchip_vpu2_vdpu_irq()
360 vdpu_write(vpu, G1_REG_INTERRUPT_DEC_IRQ_DIS, G1_REG_INTERRUPT); in rk3066_vpu_dec_reset()
361 vdpu_write(vpu, G1_REG_CONFIG_DEC_CLK_GATE_E, G1_REG_CONFIG); in rk3066_vpu_dec_reset()
377 vdpu_write(vpu, VDPU_REG_INTERRUPT_DEC_IRQ_DIS, VDPU_REG_INTERRUPT); in rockchip_vpu2_dec_reset()
378 vdpu_write(vpu, 0, VDPU_REG_EN_FLAGS); in rockchip_vpu2_dec_reset()
379 vdpu_write(vpu, 1, VDPU_REG_SOFT_RESET); in rockchip_vpu2_dec_reset()
Dhantro.h399 static inline void vdpu_write(struct hantro_dev *vpu, u32 val, u32 reg) in vdpu_write() function
409 vdpu_write(vpu, addr & 0xffffffff, offset); in hantro_write_addr()
443 vdpu_write(vpu, vdpu_read_mask(vpu, reg, val), reg->base); in hantro_reg_write_s()
Dimx8m_vpu_hw.c245 vdpu_write(vpu, 0, G1_REG_INTERRUPT); in imx8m_vpu_g1_irq()
246 vdpu_write(vpu, G1_REG_CONFIG_DEC_CLK_GATE_E, G1_REG_CONFIG); in imx8m_vpu_g1_irq()
Dhantro_g1_h264_dec.c281 vdpu_write(vpu, G1_REG_INTERRUPT_DEC_E, G1_REG_INTERRUPT); in hantro_g1_h264_dec_run()
Dhantro_g1_mpeg2_dec.c237 vdpu_write(vpu, G1_REG_INTERRUPT_DEC_E, G1_REG_INTERRUPT); in hantro_g1_mpeg2_dec_run()
Drockchip_vpu2_hw_mpeg2_dec.c245 vdpu_write(vpu, reg, VDPU_SWREG(57)); in rockchip_vpu2_mpeg2_dec_run()
Dhantro_g1_vp8_dec.c508 vdpu_write(vpu, G1_REG_INTERRUPT_DEC_E, G1_REG_INTERRUPT); in hantro_g1_vp8_dec_run()
Drockchip_vpu2_hw_h264_dec.c488 vdpu_write(vpu, reg, VDPU_SWREG(57)); in rockchip_vpu2_h264_dec_run()
Dhantro_g2_hevc_dec.c624 vdpu_write(vpu, G2_REG_INTERRUPT_DEC_E, G2_REG_INTERRUPT); in hantro_g2_hevc_dec_run()
Dhantro_g2_vp9_dec.c927 vdpu_write(ctx->dev, G2_REG_INTERRUPT_DEC_E, G2_REG_INTERRUPT); in hantro_g2_vp9_dec_run()