1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * R8A77950 processor support - PFC hardware block.
4 *
5 * Copyright (C) 2015-2017 Renesas Electronics Corporation
6 */
7
8 #include <linux/errno.h>
9 #include <linux/kernel.h>
10
11 #include "sh_pfc.h"
12
13 #define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN)
14
15 #define CPU_ALL_GP(fn, sfx) \
16 PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
17 PORT_GP_CFG_28(1, fn, sfx, CFG_FLAGS), \
18 PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
19 PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
20 PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
21 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
22 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
23 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
24 PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
25 PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
26 PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
27 PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
28
29 #define CPU_ALL_NOGP(fn) \
30 PIN_NOGP_CFG(ASEBRK, "ASEBRK", fn, CFG_FLAGS), \
31 PIN_NOGP_CFG(AVB_MDIO, "AVB_MDIO", fn, CFG_FLAGS), \
32 PIN_NOGP_CFG(AVB_RD0, "AVB_RD0", fn, CFG_FLAGS), \
33 PIN_NOGP_CFG(AVB_RD1, "AVB_RD1", fn, CFG_FLAGS), \
34 PIN_NOGP_CFG(AVB_RD2, "AVB_RD2", fn, CFG_FLAGS), \
35 PIN_NOGP_CFG(AVB_RD3, "AVB_RD3", fn, CFG_FLAGS), \
36 PIN_NOGP_CFG(AVB_RXC, "AVB_RXC", fn, CFG_FLAGS), \
37 PIN_NOGP_CFG(AVB_RX_CTL, "AVB_RX_CTL", fn, CFG_FLAGS), \
38 PIN_NOGP_CFG(AVB_TD0, "AVB_TD0", fn, CFG_FLAGS), \
39 PIN_NOGP_CFG(AVB_TD1, "AVB_TD1", fn, CFG_FLAGS), \
40 PIN_NOGP_CFG(AVB_TD2, "AVB_TD2", fn, CFG_FLAGS), \
41 PIN_NOGP_CFG(AVB_TD3, "AVB_TD3", fn, CFG_FLAGS), \
42 PIN_NOGP_CFG(AVB_TXC, "AVB_TXC", fn, CFG_FLAGS), \
43 PIN_NOGP_CFG(AVB_TXCREFCLK, "AVB_TXCREFCLK", fn, CFG_FLAGS), \
44 PIN_NOGP_CFG(AVB_TX_CTL, "AVB_TX_CTL", fn, CFG_FLAGS), \
45 PIN_NOGP_CFG(CLKOUT, "CLKOUT", fn, CFG_FLAGS), \
46 PIN_NOGP_CFG(DU_DOTCLKIN0, "DU_DOTCLKIN0", fn, CFG_FLAGS), \
47 PIN_NOGP_CFG(DU_DOTCLKIN1, "DU_DOTCLKIN1", fn, CFG_FLAGS), \
48 PIN_NOGP_CFG(DU_DOTCLKIN2, "DU_DOTCLKIN2", fn, CFG_FLAGS), \
49 PIN_NOGP_CFG(DU_DOTCLKIN3, "DU_DOTCLKIN3", fn, CFG_FLAGS), \
50 PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),\
51 PIN_NOGP_CFG(FSCLKST_N, "FSCLKST#", fn, CFG_FLAGS), \
52 PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, CFG_FLAGS), \
53 PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, CFG_FLAGS), \
54 PIN_NOGP_CFG(QSPI0_IO2, "QSPI0_IO2", fn, CFG_FLAGS), \
55 PIN_NOGP_CFG(QSPI0_IO3, "QSPI0_IO3", fn, CFG_FLAGS), \
56 PIN_NOGP_CFG(QSPI0_MISO_IO1, "QSPI0_MISO_IO1", fn, CFG_FLAGS), \
57 PIN_NOGP_CFG(QSPI0_MOSI_IO0, "QSPI0_MOSI_IO0", fn, CFG_FLAGS), \
58 PIN_NOGP_CFG(QSPI0_SPCLK, "QSPI0_SPCLK", fn, CFG_FLAGS), \
59 PIN_NOGP_CFG(QSPI0_SSL, "QSPI0_SSL", fn, CFG_FLAGS), \
60 PIN_NOGP_CFG(QSPI1_IO2, "QSPI1_IO2", fn, CFG_FLAGS), \
61 PIN_NOGP_CFG(QSPI1_IO3, "QSPI1_IO3", fn, CFG_FLAGS), \
62 PIN_NOGP_CFG(QSPI1_MISO_IO1, "QSPI1_MISO_IO1", fn, CFG_FLAGS), \
63 PIN_NOGP_CFG(QSPI1_MOSI_IO0, "QSPI1_MOSI_IO0", fn, CFG_FLAGS), \
64 PIN_NOGP_CFG(QSPI1_SPCLK, "QSPI1_SPCLK", fn, CFG_FLAGS), \
65 PIN_NOGP_CFG(QSPI1_SSL, "QSPI1_SSL", fn, CFG_FLAGS), \
66 PIN_NOGP_CFG(RPC_INT_N, "RPC_INT#", fn, CFG_FLAGS), \
67 PIN_NOGP_CFG(RPC_RESET_N, "RPC_RESET#", fn, CFG_FLAGS), \
68 PIN_NOGP_CFG(RPC_WP_N, "RPC_WP#", fn, CFG_FLAGS), \
69 PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
70 PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
71 PIN_NOGP_CFG(TDO, "TDO", fn, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
72 PIN_NOGP_CFG(TMS, "TMS", fn, CFG_FLAGS), \
73 PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN)
74
75 /*
76 * F_() : just information
77 * FM() : macro for FN_xxx / xxx_MARK
78 */
79
80 /* GPSR0 */
81 #define GPSR0_15 F_(D15, IP7_11_8)
82 #define GPSR0_14 F_(D14, IP7_7_4)
83 #define GPSR0_13 F_(D13, IP7_3_0)
84 #define GPSR0_12 F_(D12, IP6_31_28)
85 #define GPSR0_11 F_(D11, IP6_27_24)
86 #define GPSR0_10 F_(D10, IP6_23_20)
87 #define GPSR0_9 F_(D9, IP6_19_16)
88 #define GPSR0_8 F_(D8, IP6_15_12)
89 #define GPSR0_7 F_(D7, IP6_11_8)
90 #define GPSR0_6 F_(D6, IP6_7_4)
91 #define GPSR0_5 F_(D5, IP6_3_0)
92 #define GPSR0_4 F_(D4, IP5_31_28)
93 #define GPSR0_3 F_(D3, IP5_27_24)
94 #define GPSR0_2 F_(D2, IP5_23_20)
95 #define GPSR0_1 F_(D1, IP5_19_16)
96 #define GPSR0_0 F_(D0, IP5_15_12)
97
98 /* GPSR1 */
99 #define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8)
100 #define GPSR1_26 F_(WE1_N, IP5_7_4)
101 #define GPSR1_25 F_(WE0_N, IP5_3_0)
102 #define GPSR1_24 F_(RD_WR_N, IP4_31_28)
103 #define GPSR1_23 F_(RD_N, IP4_27_24)
104 #define GPSR1_22 F_(BS_N, IP4_23_20)
105 #define GPSR1_21 F_(CS1_N_A26, IP4_19_16)
106 #define GPSR1_20 F_(CS0_N, IP4_15_12)
107 #define GPSR1_19 F_(A19, IP4_11_8)
108 #define GPSR1_18 F_(A18, IP4_7_4)
109 #define GPSR1_17 F_(A17, IP4_3_0)
110 #define GPSR1_16 F_(A16, IP3_31_28)
111 #define GPSR1_15 F_(A15, IP3_27_24)
112 #define GPSR1_14 F_(A14, IP3_23_20)
113 #define GPSR1_13 F_(A13, IP3_19_16)
114 #define GPSR1_12 F_(A12, IP3_15_12)
115 #define GPSR1_11 F_(A11, IP3_11_8)
116 #define GPSR1_10 F_(A10, IP3_7_4)
117 #define GPSR1_9 F_(A9, IP3_3_0)
118 #define GPSR1_8 F_(A8, IP2_31_28)
119 #define GPSR1_7 F_(A7, IP2_27_24)
120 #define GPSR1_6 F_(A6, IP2_23_20)
121 #define GPSR1_5 F_(A5, IP2_19_16)
122 #define GPSR1_4 F_(A4, IP2_15_12)
123 #define GPSR1_3 F_(A3, IP2_11_8)
124 #define GPSR1_2 F_(A2, IP2_7_4)
125 #define GPSR1_1 F_(A1, IP2_3_0)
126 #define GPSR1_0 F_(A0, IP1_31_28)
127
128 /* GPSR2 */
129 #define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20)
130 #define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16)
131 #define GPSR2_12 F_(AVB_LINK, IP0_15_12)
132 #define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8)
133 #define GPSR2_10 F_(AVB_MAGIC, IP0_7_4)
134 #define GPSR2_9 F_(AVB_MDC, IP0_3_0)
135 #define GPSR2_8 F_(PWM2_A, IP1_27_24)
136 #define GPSR2_7 F_(PWM1_A, IP1_23_20)
137 #define GPSR2_6 F_(PWM0, IP1_19_16)
138 #define GPSR2_5 F_(IRQ5, IP1_15_12)
139 #define GPSR2_4 F_(IRQ4, IP1_11_8)
140 #define GPSR2_3 F_(IRQ3, IP1_7_4)
141 #define GPSR2_2 F_(IRQ2, IP1_3_0)
142 #define GPSR2_1 F_(IRQ1, IP0_31_28)
143 #define GPSR2_0 F_(IRQ0, IP0_27_24)
144
145 /* GPSR3 */
146 #define GPSR3_15 F_(SD1_WP, IP10_23_20)
147 #define GPSR3_14 F_(SD1_CD, IP10_19_16)
148 #define GPSR3_13 F_(SD0_WP, IP10_15_12)
149 #define GPSR3_12 F_(SD0_CD, IP10_11_8)
150 #define GPSR3_11 F_(SD1_DAT3, IP8_31_28)
151 #define GPSR3_10 F_(SD1_DAT2, IP8_27_24)
152 #define GPSR3_9 F_(SD1_DAT1, IP8_23_20)
153 #define GPSR3_8 F_(SD1_DAT0, IP8_19_16)
154 #define GPSR3_7 F_(SD1_CMD, IP8_15_12)
155 #define GPSR3_6 F_(SD1_CLK, IP8_11_8)
156 #define GPSR3_5 F_(SD0_DAT3, IP8_7_4)
157 #define GPSR3_4 F_(SD0_DAT2, IP8_3_0)
158 #define GPSR3_3 F_(SD0_DAT1, IP7_31_28)
159 #define GPSR3_2 F_(SD0_DAT0, IP7_27_24)
160 #define GPSR3_1 F_(SD0_CMD, IP7_23_20)
161 #define GPSR3_0 F_(SD0_CLK, IP7_19_16)
162
163 /* GPSR4 */
164 #define GPSR4_17 FM(SD3_DS)
165 #define GPSR4_16 F_(SD3_DAT7, IP10_7_4)
166 #define GPSR4_15 F_(SD3_DAT6, IP10_3_0)
167 #define GPSR4_14 F_(SD3_DAT5, IP9_31_28)
168 #define GPSR4_13 F_(SD3_DAT4, IP9_27_24)
169 #define GPSR4_12 FM(SD3_DAT3)
170 #define GPSR4_11 FM(SD3_DAT2)
171 #define GPSR4_10 FM(SD3_DAT1)
172 #define GPSR4_9 FM(SD3_DAT0)
173 #define GPSR4_8 FM(SD3_CMD)
174 #define GPSR4_7 FM(SD3_CLK)
175 #define GPSR4_6 F_(SD2_DS, IP9_23_20)
176 #define GPSR4_5 F_(SD2_DAT3, IP9_19_16)
177 #define GPSR4_4 F_(SD2_DAT2, IP9_15_12)
178 #define GPSR4_3 F_(SD2_DAT1, IP9_11_8)
179 #define GPSR4_2 F_(SD2_DAT0, IP9_7_4)
180 #define GPSR4_1 FM(SD2_CMD)
181 #define GPSR4_0 F_(SD2_CLK, IP9_3_0)
182
183 /* GPSR5 */
184 #define GPSR5_25 F_(MLB_DAT, IP13_19_16)
185 #define GPSR5_24 F_(MLB_SIG, IP13_15_12)
186 #define GPSR5_23 F_(MLB_CLK, IP13_11_8)
187 #define GPSR5_22 FM(MSIOF0_RXD)
188 #define GPSR5_21 F_(MSIOF0_SS2, IP13_7_4)
189 #define GPSR5_20 FM(MSIOF0_TXD)
190 #define GPSR5_19 F_(MSIOF0_SS1, IP13_3_0)
191 #define GPSR5_18 F_(MSIOF0_SYNC, IP12_31_28)
192 #define GPSR5_17 FM(MSIOF0_SCK)
193 #define GPSR5_16 F_(HRTS0_N, IP12_27_24)
194 #define GPSR5_15 F_(HCTS0_N, IP12_23_20)
195 #define GPSR5_14 F_(HTX0, IP12_19_16)
196 #define GPSR5_13 F_(HRX0, IP12_15_12)
197 #define GPSR5_12 F_(HSCK0, IP12_11_8)
198 #define GPSR5_11 F_(RX2_A, IP12_7_4)
199 #define GPSR5_10 F_(TX2_A, IP12_3_0)
200 #define GPSR5_9 F_(SCK2, IP11_31_28)
201 #define GPSR5_8 F_(RTS1_N, IP11_27_24)
202 #define GPSR5_7 F_(CTS1_N, IP11_23_20)
203 #define GPSR5_6 F_(TX1_A, IP11_19_16)
204 #define GPSR5_5 F_(RX1_A, IP11_15_12)
205 #define GPSR5_4 F_(RTS0_N, IP11_11_8)
206 #define GPSR5_3 F_(CTS0_N, IP11_7_4)
207 #define GPSR5_2 F_(TX0, IP11_3_0)
208 #define GPSR5_1 F_(RX0, IP10_31_28)
209 #define GPSR5_0 F_(SCK0, IP10_27_24)
210
211 /* GPSR6 */
212 #define GPSR6_31 F_(USB31_OVC, IP17_7_4)
213 #define GPSR6_30 F_(USB31_PWEN, IP17_3_0)
214 #define GPSR6_29 F_(USB30_OVC, IP16_31_28)
215 #define GPSR6_28 F_(USB30_PWEN, IP16_27_24)
216 #define GPSR6_27 F_(USB1_OVC, IP16_23_20)
217 #define GPSR6_26 F_(USB1_PWEN, IP16_19_16)
218 #define GPSR6_25 F_(USB0_OVC, IP16_15_12)
219 #define GPSR6_24 F_(USB0_PWEN, IP16_11_8)
220 #define GPSR6_23 F_(AUDIO_CLKB_B, IP16_7_4)
221 #define GPSR6_22 F_(AUDIO_CLKA_A, IP16_3_0)
222 #define GPSR6_21 F_(SSI_SDATA9_A, IP15_31_28)
223 #define GPSR6_20 F_(SSI_SDATA8, IP15_27_24)
224 #define GPSR6_19 F_(SSI_SDATA7, IP15_23_20)
225 #define GPSR6_18 F_(SSI_WS78, IP15_19_16)
226 #define GPSR6_17 F_(SSI_SCK78, IP15_15_12)
227 #define GPSR6_16 F_(SSI_SDATA6, IP15_11_8)
228 #define GPSR6_15 F_(SSI_WS6, IP15_7_4)
229 #define GPSR6_14 F_(SSI_SCK6, IP15_3_0)
230 #define GPSR6_13 FM(SSI_SDATA5)
231 #define GPSR6_12 FM(SSI_WS5)
232 #define GPSR6_11 FM(SSI_SCK5)
233 #define GPSR6_10 F_(SSI_SDATA4, IP14_31_28)
234 #define GPSR6_9 F_(SSI_WS4, IP14_27_24)
235 #define GPSR6_8 F_(SSI_SCK4, IP14_23_20)
236 #define GPSR6_7 F_(SSI_SDATA3, IP14_19_16)
237 #define GPSR6_6 F_(SSI_WS349, IP14_15_12)
238 #define GPSR6_5 F_(SSI_SCK349, IP14_11_8)
239 #define GPSR6_4 F_(SSI_SDATA2_A, IP14_7_4)
240 #define GPSR6_3 F_(SSI_SDATA1_A, IP14_3_0)
241 #define GPSR6_2 F_(SSI_SDATA0, IP13_31_28)
242 #define GPSR6_1 F_(SSI_WS01239, IP13_27_24)
243 #define GPSR6_0 F_(SSI_SCK01239, IP13_23_20)
244
245 /* GPSR7 */
246 #define GPSR7_3 FM(GP7_03)
247 #define GPSR7_2 FM(GP7_02)
248 #define GPSR7_1 FM(AVS2)
249 #define GPSR7_0 FM(AVS1)
250
251
252 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
253 #define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
254 #define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
255 #define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
256 #define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
257 #define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
258 #define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
259 #define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
260 #define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
261 #define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
262 #define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) FM(A25) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263 #define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) FM(A24) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264 #define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) FM(A23) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
265 #define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)FM(A22) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
266 #define IP1_23_20 FM(PWM1_A) F_(0, 0) FM(A21) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
267 #define IP1_27_24 FM(PWM2_A) F_(0, 0) FM(A20) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
268 #define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
269 #define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
270 #define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
271 #define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
272
273 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
274 #define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
275 #define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
276 #define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
277 #define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
278 #define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279 #define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280 #define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
281 #define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
282 #define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
283 #define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
284 #define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
285 #define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
286 #define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
287 #define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
288 #define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
289 #define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
290 #define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
291 #define IP4_19_16 FM(CS1_N_A26) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292 #define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293 #define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294 #define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295 #define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
296 #define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
297 #define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
298 #define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
299 #define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
300 #define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301 #define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
302 #define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
303 #define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
304 #define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305 #define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
306 #define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
307 #define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
308 #define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
309 #define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_C) FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
310 #define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
311 #define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
312 #define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
313 #define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
314 #define IP7_15_12 FM(FSCLKST) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
315 #define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
316
317 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
318 #define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
319 #define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
320 #define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
321 #define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
322 #define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
323 #define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
324 #define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) F_(0, 0) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
325 #define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) F_(0, 0) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
326 #define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
327 #define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) F_(0, 0) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
328 #define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) F_(0, 0) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
329 #define IP9_3_0 FM(SD2_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
330 #define IP9_7_4 FM(SD2_DAT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
331 #define IP9_11_8 FM(SD2_DAT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
332 #define IP9_15_12 FM(SD2_DAT2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
333 #define IP9_19_16 FM(SD2_DAT3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
334 #define IP9_23_20 FM(SD2_DS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
335 #define IP9_27_24 FM(SD3_DAT4) FM(SD2_CD_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
336 #define IP9_31_28 FM(SD3_DAT5) FM(SD2_WP_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
337 #define IP10_3_0 FM(SD3_DAT6) FM(SD3_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
338 #define IP10_7_4 FM(SD3_DAT7) FM(SD3_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
339 #define IP10_11_8 FM(SD0_CD) F_(0, 0) F_(0, 0) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
340 #define IP10_15_12 FM(SD0_WP) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
341 #define IP10_19_16 FM(SD1_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
342 #define IP10_23_20 FM(SD1_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
343 #define IP10_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
344 #define IP10_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
345 #define IP11_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
346 #define IP11_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
347 #define IP11_11_8 FM(RTS0_N) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
348 #define IP11_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
349 #define IP11_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
350 #define IP11_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
351 #define IP11_27_24 FM(RTS1_N) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
352 #define IP11_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
353 #define IP12_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
354 #define IP12_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
355 #define IP12_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
356 #define IP12_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
357 #define IP12_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
358 #define IP12_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
359 #define IP12_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
360
361 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
362 #define IP12_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
363 #define IP13_3_0 FM(MSIOF0_SS1) FM(RX5) F_(0, 0) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
364 #define IP13_7_4 FM(MSIOF0_SS2) FM(TX5) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
365 #define IP13_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
366 #define IP13_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
367 #define IP13_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
368 #define IP13_23_20 FM(SSI_SCK01239) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
369 #define IP13_27_24 FM(SSI_WS01239) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
370 #define IP13_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
371 #define IP14_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
372 #define IP14_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
373 #define IP14_11_8 FM(SSI_SCK349) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
374 #define IP14_15_12 FM(SSI_WS349) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
375 #define IP14_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
376 #define IP14_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
377 #define IP14_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
378 #define IP14_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
379 #define IP15_3_0 FM(SSI_SCK6) FM(USB2_PWEN) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
380 #define IP15_7_4 FM(SSI_WS6) FM(USB2_OVC) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
381 #define IP15_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
382 #define IP15_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
383 #define IP15_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
384 #define IP15_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
385 #define IP15_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
386 #define IP15_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
387 #define IP16_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
388 #define IP16_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
389 #define IP16_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
390 #define IP16_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
391 #define IP16_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
392 #define IP16_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
393 #define IP16_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
394 #define IP16_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_B) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
395 #define IP17_3_0 FM(USB31_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
396 #define IP17_7_4 FM(USB31_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
397
398 #define PINMUX_GPSR \
399 \
400 GPSR6_31 \
401 GPSR6_30 \
402 GPSR6_29 \
403 GPSR6_28 \
404 GPSR1_27 GPSR6_27 \
405 GPSR1_26 GPSR6_26 \
406 GPSR1_25 GPSR5_25 GPSR6_25 \
407 GPSR1_24 GPSR5_24 GPSR6_24 \
408 GPSR1_23 GPSR5_23 GPSR6_23 \
409 GPSR1_22 GPSR5_22 GPSR6_22 \
410 GPSR1_21 GPSR5_21 GPSR6_21 \
411 GPSR1_20 GPSR5_20 GPSR6_20 \
412 GPSR1_19 GPSR5_19 GPSR6_19 \
413 GPSR1_18 GPSR5_18 GPSR6_18 \
414 GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \
415 GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \
416 GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \
417 GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \
418 GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \
419 GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \
420 GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \
421 GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \
422 GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
423 GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
424 GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
425 GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
426 GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
427 GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
428 GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \
429 GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \
430 GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \
431 GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0
432
433 #define PINMUX_IPSR \
434 \
435 FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
436 FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
437 FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
438 FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
439 FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
440 FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
441 FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
442 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
443 \
444 FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
445 FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
446 FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
447 FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 FM(IP7_15_12) IP7_15_12 \
448 FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
449 FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
450 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
451 FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
452 \
453 FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
454 FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
455 FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
456 FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
457 FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
458 FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
459 FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
460 FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
461 \
462 FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \
463 FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \
464 FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \
465 FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \
466 FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \
467 FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \
468 FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \
469 FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \
470 \
471 FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 \
472 FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 \
473 FM(IP16_11_8) IP16_11_8 \
474 FM(IP16_15_12) IP16_15_12 \
475 FM(IP16_19_16) IP16_19_16 \
476 FM(IP16_23_20) IP16_23_20 \
477 FM(IP16_27_24) IP16_27_24 \
478 FM(IP16_31_28) IP16_31_28
479
480 /* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
481 #define MOD_SEL0_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3)
482 #define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3)
483 #define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0)
484 #define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1)
485 #define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1)
486 #define MOD_SEL0_21_20 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0)
487 #define MOD_SEL0_19 FM(SEL_I2C2_0) FM(SEL_I2C2_1)
488 #define MOD_SEL0_18 FM(SEL_I2C1_0) FM(SEL_I2C1_1)
489 #define MOD_SEL0_17 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1)
490 #define MOD_SEL0_16_15 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3)
491 #define MOD_SEL0_14 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1)
492 #define MOD_SEL0_13 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1)
493 #define MOD_SEL0_12 FM(SEL_FSO_0) FM(SEL_FSO_1)
494 #define MOD_SEL0_11 FM(SEL_FM_0) FM(SEL_FM_1)
495 #define MOD_SEL0_10 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1)
496 #define MOD_SEL0_9 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1)
497 #define MOD_SEL0_8 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
498 #define MOD_SEL0_7_6 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
499 #define MOD_SEL0_5_4 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
500 #define MOD_SEL0_3 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
501 #define MOD_SEL0_2_1 FM(SEL_ADG_0) FM(SEL_ADG_1) FM(SEL_ADG_2) FM(SEL_ADG_3)
502
503 /* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
504 #define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
505 #define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0)
506 #define MOD_SEL1_26 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1)
507 #define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3)
508 #define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0)
509 #define MOD_SEL1_20 FM(SEL_SSI_0) FM(SEL_SSI_1)
510 #define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1)
511 #define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3)
512 #define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1)
513 #define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0)
514 #define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1)
515 #define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1)
516 #define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
517 #define MOD_SEL1_10 FM(SEL_SATA_0) FM(SEL_SATA_1)
518 #define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1)
519 #define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1)
520 #define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1)
521 #define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1)
522 #define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
523 #define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
524 #define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
525 #define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
526
527 /* MOD_SEL2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */
528 #define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1)
529 #define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1)
530 #define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1)
531 #define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
532
533 #define PINMUX_MOD_SELS\
534 \
535 MOD_SEL1_31_30 MOD_SEL2_31 \
536 MOD_SEL0_30_29 MOD_SEL2_30 \
537 MOD_SEL1_29_28_27 MOD_SEL2_29 \
538 MOD_SEL0_28_27 \
539 \
540 MOD_SEL0_26_25_24 MOD_SEL1_26 \
541 MOD_SEL1_25_24 \
542 \
543 MOD_SEL0_23 MOD_SEL1_23_22_21 \
544 MOD_SEL0_22 \
545 MOD_SEL0_21_20 \
546 MOD_SEL1_20 \
547 MOD_SEL0_19 MOD_SEL1_19 \
548 MOD_SEL0_18 MOD_SEL1_18_17 \
549 MOD_SEL0_17 \
550 MOD_SEL0_16_15 MOD_SEL1_16 \
551 MOD_SEL1_15_14 \
552 MOD_SEL0_14 \
553 MOD_SEL0_13 MOD_SEL1_13 \
554 MOD_SEL0_12 MOD_SEL1_12 \
555 MOD_SEL0_11 MOD_SEL1_11 \
556 MOD_SEL0_10 MOD_SEL1_10 \
557 MOD_SEL0_9 MOD_SEL1_9 \
558 MOD_SEL0_8 \
559 MOD_SEL0_7_6 \
560 MOD_SEL1_6 \
561 MOD_SEL0_5_4 MOD_SEL1_5 \
562 MOD_SEL1_4 \
563 MOD_SEL0_3 MOD_SEL1_3 \
564 MOD_SEL0_2_1 MOD_SEL1_2 \
565 MOD_SEL1_1 \
566 MOD_SEL1_0 MOD_SEL2_0
567
568 /*
569 * These pins are not able to be muxed but have other properties
570 * that can be set, such as drive-strength or pull-up/pull-down enable.
571 */
572 #define PINMUX_STATIC \
573 FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
574 FM(QSPI0_IO2) FM(QSPI0_IO3) \
575 FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
576 FM(QSPI1_IO2) FM(QSPI1_IO3) \
577 FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
578 FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
579 FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
580 FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
581 FM(CLKOUT) FM(PRESETOUT) \
582 FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) FM(DU_DOTCLKIN3) \
583 FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
584
585 #define PINMUX_PHYS \
586 FM(SCL0) FM(SDA0) FM(SCL3) FM(SDA3) FM(SCL5) FM(SDA5)
587
588 enum {
589 PINMUX_RESERVED = 0,
590
591 PINMUX_DATA_BEGIN,
592 GP_ALL(DATA),
593 PINMUX_DATA_END,
594
595 #define F_(x, y)
596 #define FM(x) FN_##x,
597 PINMUX_FUNCTION_BEGIN,
598 GP_ALL(FN),
599 PINMUX_GPSR
600 PINMUX_IPSR
601 PINMUX_MOD_SELS
602 PINMUX_FUNCTION_END,
603 #undef F_
604 #undef FM
605
606 #define F_(x, y)
607 #define FM(x) x##_MARK,
608 PINMUX_MARK_BEGIN,
609 PINMUX_GPSR
610 PINMUX_IPSR
611 PINMUX_MOD_SELS
612 PINMUX_STATIC
613 PINMUX_PHYS
614 PINMUX_MARK_END,
615 #undef F_
616 #undef FM
617 };
618
619 static const u16 pinmux_data[] = {
620 PINMUX_DATA_GP_ALL(),
621
622 PINMUX_SINGLE(AVS1),
623 PINMUX_SINGLE(AVS2),
624 PINMUX_SINGLE(GP7_02),
625 PINMUX_SINGLE(GP7_03),
626 PINMUX_SINGLE(MSIOF0_RXD),
627 PINMUX_SINGLE(MSIOF0_SCK),
628 PINMUX_SINGLE(MSIOF0_TXD),
629 PINMUX_SINGLE(SD2_CMD),
630 PINMUX_SINGLE(SD3_CLK),
631 PINMUX_SINGLE(SD3_CMD),
632 PINMUX_SINGLE(SD3_DAT0),
633 PINMUX_SINGLE(SD3_DAT1),
634 PINMUX_SINGLE(SD3_DAT2),
635 PINMUX_SINGLE(SD3_DAT3),
636 PINMUX_SINGLE(SD3_DS),
637 PINMUX_SINGLE(SSI_SCK5),
638 PINMUX_SINGLE(SSI_SDATA5),
639 PINMUX_SINGLE(SSI_WS5),
640
641 /* IPSR0 */
642 PINMUX_IPSR_GPSR(IP0_3_0, AVB_MDC),
643 PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SS2_C, SEL_MSIOF2_2),
644
645 PINMUX_IPSR_GPSR(IP0_7_4, AVB_MAGIC),
646 PINMUX_IPSR_MSEL(IP0_7_4, MSIOF2_SS1_C, SEL_MSIOF2_2),
647 PINMUX_IPSR_MSEL(IP0_7_4, SCK4_A, SEL_SCIF4_0),
648
649 PINMUX_IPSR_GPSR(IP0_11_8, AVB_PHY_INT),
650 PINMUX_IPSR_MSEL(IP0_11_8, MSIOF2_SYNC_C, SEL_MSIOF2_2),
651 PINMUX_IPSR_MSEL(IP0_11_8, RX4_A, SEL_SCIF4_0),
652
653 PINMUX_IPSR_GPSR(IP0_15_12, AVB_LINK),
654 PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2),
655 PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0),
656
657 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
658 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, MSIOF2_RXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
659 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, CTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
660 PINMUX_IPSR_PHYS(IP0_19_16, SCL5, I2C_SEL_5_1),
661
662 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
663 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
664 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
665 PINMUX_IPSR_PHYS(IP0_23_20, SDA5, I2C_SEL_5_1),
666
667 PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
668 PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
669 PINMUX_IPSR_GPSR(IP0_27_24, DU_CDE),
670 PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA0_B, SEL_VIN4_1),
671 PINMUX_IPSR_MSEL(IP0_27_24, CAN0_TX_B, SEL_RCAN0_1),
672 PINMUX_IPSR_MSEL(IP0_27_24, CANFD0_TX_B, SEL_CANFD0_1),
673
674 PINMUX_IPSR_GPSR(IP0_31_28, IRQ1),
675 PINMUX_IPSR_GPSR(IP0_31_28, QPOLA),
676 PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP),
677 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1),
678 PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1),
679 PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1),
680
681 /* IPSR1 */
682 PINMUX_IPSR_GPSR(IP1_3_0, IRQ2),
683 PINMUX_IPSR_GPSR(IP1_3_0, QCPV_QDE),
684 PINMUX_IPSR_GPSR(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE),
685 PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1),
686 PINMUX_IPSR_MSEL(IP1_3_0, PWM3_B, SEL_PWM3_1),
687
688 PINMUX_IPSR_GPSR(IP1_7_4, IRQ3),
689 PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE),
690 PINMUX_IPSR_GPSR(IP1_7_4, A25),
691 PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1),
692 PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1),
693 PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1),
694
695 PINMUX_IPSR_GPSR(IP1_11_8, IRQ4),
696 PINMUX_IPSR_GPSR(IP1_11_8, QSTH_QHS),
697 PINMUX_IPSR_GPSR(IP1_11_8, A24),
698 PINMUX_IPSR_GPSR(IP1_11_8, DU_EXHSYNC_DU_HSYNC),
699 PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1),
700 PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1),
701
702 PINMUX_IPSR_GPSR(IP1_15_12, IRQ5),
703 PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE),
704 PINMUX_IPSR_GPSR(IP1_15_12, A23),
705 PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC),
706 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1),
707 PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1),
708
709 PINMUX_IPSR_GPSR(IP1_19_16, PWM0),
710 PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS),
711 PINMUX_IPSR_GPSR(IP1_19_16, A22),
712 PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1),
713 PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1),
714
715 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, PWM1_A, I2C_SEL_3_0, SEL_PWM1_0),
716 PINMUX_IPSR_MSEL(IP1_23_20, A21, I2C_SEL_3_0),
717 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
718 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B, I2C_SEL_3_0, SEL_VIN4_1),
719 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B, I2C_SEL_3_0, SEL_IEBUS_1),
720 PINMUX_IPSR_PHYS(IP1_23_20, SCL3, I2C_SEL_3_1),
721
722 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A, I2C_SEL_3_0, SEL_PWM2_0),
723 PINMUX_IPSR_MSEL(IP1_27_24, A20, I2C_SEL_3_0),
724 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
725 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, IETX_B, I2C_SEL_3_0, SEL_IEBUS_1),
726 PINMUX_IPSR_PHYS(IP1_27_24, SDA3, I2C_SEL_3_1),
727
728 PINMUX_IPSR_GPSR(IP1_31_28, A0),
729 PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16),
730 PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SYNC_B, SEL_MSIOF3_1),
731 PINMUX_IPSR_GPSR(IP1_31_28, VI4_DATA8),
732 PINMUX_IPSR_GPSR(IP1_31_28, DU_DB0),
733 PINMUX_IPSR_MSEL(IP1_31_28, PWM3_A, SEL_PWM3_0),
734
735 /* IPSR2 */
736 PINMUX_IPSR_GPSR(IP2_3_0, A1),
737 PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT17),
738 PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_TXD_B, SEL_MSIOF3_1),
739 PINMUX_IPSR_GPSR(IP2_3_0, VI4_DATA9),
740 PINMUX_IPSR_GPSR(IP2_3_0, DU_DB1),
741 PINMUX_IPSR_MSEL(IP2_3_0, PWM4_A, SEL_PWM4_0),
742
743 PINMUX_IPSR_GPSR(IP2_7_4, A2),
744 PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT18),
745 PINMUX_IPSR_MSEL(IP2_7_4, MSIOF3_SCK_B, SEL_MSIOF3_1),
746 PINMUX_IPSR_GPSR(IP2_7_4, VI4_DATA10),
747 PINMUX_IPSR_GPSR(IP2_7_4, DU_DB2),
748 PINMUX_IPSR_MSEL(IP2_7_4, PWM5_A, SEL_PWM5_0),
749
750 PINMUX_IPSR_GPSR(IP2_11_8, A3),
751 PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT19),
752 PINMUX_IPSR_MSEL(IP2_11_8, MSIOF3_RXD_B, SEL_MSIOF3_1),
753 PINMUX_IPSR_GPSR(IP2_11_8, VI4_DATA11),
754 PINMUX_IPSR_GPSR(IP2_11_8, DU_DB3),
755 PINMUX_IPSR_MSEL(IP2_11_8, PWM6_A, SEL_PWM6_0),
756
757 PINMUX_IPSR_GPSR(IP2_15_12, A4),
758 PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT20),
759 PINMUX_IPSR_MSEL(IP2_15_12, MSIOF3_SS1_B, SEL_MSIOF3_1),
760 PINMUX_IPSR_GPSR(IP2_15_12, VI4_DATA12),
761 PINMUX_IPSR_GPSR(IP2_15_12, VI5_DATA12),
762 PINMUX_IPSR_GPSR(IP2_15_12, DU_DB4),
763
764 PINMUX_IPSR_GPSR(IP2_19_16, A5),
765 PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT21),
766 PINMUX_IPSR_MSEL(IP2_19_16, MSIOF3_SS2_B, SEL_MSIOF3_1),
767 PINMUX_IPSR_MSEL(IP2_19_16, SCK4_B, SEL_SCIF4_1),
768 PINMUX_IPSR_GPSR(IP2_19_16, VI4_DATA13),
769 PINMUX_IPSR_GPSR(IP2_19_16, VI5_DATA13),
770 PINMUX_IPSR_GPSR(IP2_19_16, DU_DB5),
771
772 PINMUX_IPSR_GPSR(IP2_23_20, A6),
773 PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT22),
774 PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_SS1_A, SEL_MSIOF2_0),
775 PINMUX_IPSR_MSEL(IP2_23_20, RX4_B, SEL_SCIF4_1),
776 PINMUX_IPSR_GPSR(IP2_23_20, VI4_DATA14),
777 PINMUX_IPSR_GPSR(IP2_23_20, VI5_DATA14),
778 PINMUX_IPSR_GPSR(IP2_23_20, DU_DB6),
779
780 PINMUX_IPSR_GPSR(IP2_27_24, A7),
781 PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT23),
782 PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SS2_A, SEL_MSIOF2_0),
783 PINMUX_IPSR_MSEL(IP2_27_24, TX4_B, SEL_SCIF4_1),
784 PINMUX_IPSR_GPSR(IP2_27_24, VI4_DATA15),
785 PINMUX_IPSR_GPSR(IP2_27_24, VI5_DATA15),
786 PINMUX_IPSR_GPSR(IP2_27_24, DU_DB7),
787
788 PINMUX_IPSR_GPSR(IP2_31_28, A8),
789 PINMUX_IPSR_MSEL(IP2_31_28, RX3_B, SEL_SCIF3_1),
790 PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0),
791 PINMUX_IPSR_MSEL(IP2_31_28, HRX4_B, SEL_HSCIF4_1),
792 PINMUX_IPSR_MSEL(IP2_31_28, SDA6_A, SEL_I2C6_0),
793 PINMUX_IPSR_MSEL(IP2_31_28, AVB_AVTP_MATCH_B, SEL_ETHERAVB_1),
794 PINMUX_IPSR_MSEL(IP2_31_28, PWM1_B, SEL_PWM1_1),
795
796 /* IPSR3 */
797 PINMUX_IPSR_GPSR(IP3_3_0, A9),
798 PINMUX_IPSR_MSEL(IP3_3_0, MSIOF2_SCK_A, SEL_MSIOF2_0),
799 PINMUX_IPSR_MSEL(IP3_3_0, CTS4_N_B, SEL_SCIF4_1),
800 PINMUX_IPSR_GPSR(IP3_3_0, VI5_VSYNC_N),
801
802 PINMUX_IPSR_GPSR(IP3_7_4, A10),
803 PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0),
804 PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_B, SEL_SCIF4_1),
805 PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N),
806
807 PINMUX_IPSR_GPSR(IP3_11_8, A11),
808 PINMUX_IPSR_MSEL(IP3_11_8, TX3_B, SEL_SCIF3_1),
809 PINMUX_IPSR_MSEL(IP3_11_8, MSIOF2_TXD_A, SEL_MSIOF2_0),
810 PINMUX_IPSR_MSEL(IP3_11_8, HTX4_B, SEL_HSCIF4_1),
811 PINMUX_IPSR_GPSR(IP3_11_8, HSCK4),
812 PINMUX_IPSR_GPSR(IP3_11_8, VI5_FIELD),
813 PINMUX_IPSR_MSEL(IP3_11_8, SCL6_A, SEL_I2C6_0),
814 PINMUX_IPSR_MSEL(IP3_11_8, AVB_AVTP_CAPTURE_B, SEL_ETHERAVB_1),
815 PINMUX_IPSR_MSEL(IP3_11_8, PWM2_B, SEL_PWM2_1),
816
817 PINMUX_IPSR_GPSR(IP3_15_12, A12),
818 PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT12),
819 PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SCK_C, SEL_MSIOF3_2),
820 PINMUX_IPSR_MSEL(IP3_15_12, HRX4_A, SEL_HSCIF4_0),
821 PINMUX_IPSR_GPSR(IP3_15_12, VI5_DATA8),
822 PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4),
823
824 PINMUX_IPSR_GPSR(IP3_19_16, A13),
825 PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT13),
826 PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SYNC_C, SEL_MSIOF3_2),
827 PINMUX_IPSR_MSEL(IP3_19_16, HTX4_A, SEL_HSCIF4_0),
828 PINMUX_IPSR_GPSR(IP3_19_16, VI5_DATA9),
829 PINMUX_IPSR_GPSR(IP3_19_16, DU_DG5),
830
831 PINMUX_IPSR_GPSR(IP3_23_20, A14),
832 PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT14),
833 PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_C, SEL_MSIOF3_2),
834 PINMUX_IPSR_GPSR(IP3_23_20, HCTS4_N),
835 PINMUX_IPSR_GPSR(IP3_23_20, VI5_DATA10),
836 PINMUX_IPSR_GPSR(IP3_23_20, DU_DG6),
837
838 PINMUX_IPSR_GPSR(IP3_27_24, A15),
839 PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT15),
840 PINMUX_IPSR_MSEL(IP3_27_24, MSIOF3_TXD_C, SEL_MSIOF3_2),
841 PINMUX_IPSR_GPSR(IP3_27_24, HRTS4_N),
842 PINMUX_IPSR_GPSR(IP3_27_24, VI5_DATA11),
843 PINMUX_IPSR_GPSR(IP3_27_24, DU_DG7),
844
845 PINMUX_IPSR_GPSR(IP3_31_28, A16),
846 PINMUX_IPSR_GPSR(IP3_31_28, LCDOUT8),
847 PINMUX_IPSR_GPSR(IP3_31_28, VI4_FIELD),
848 PINMUX_IPSR_GPSR(IP3_31_28, DU_DG0),
849
850 /* IPSR4 */
851 PINMUX_IPSR_GPSR(IP4_3_0, A17),
852 PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT9),
853 PINMUX_IPSR_GPSR(IP4_3_0, VI4_VSYNC_N),
854 PINMUX_IPSR_GPSR(IP4_3_0, DU_DG1),
855
856 PINMUX_IPSR_GPSR(IP4_7_4, A18),
857 PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT10),
858 PINMUX_IPSR_GPSR(IP4_7_4, VI4_HSYNC_N),
859 PINMUX_IPSR_GPSR(IP4_7_4, DU_DG2),
860
861 PINMUX_IPSR_GPSR(IP4_11_8, A19),
862 PINMUX_IPSR_GPSR(IP4_11_8, LCDOUT11),
863 PINMUX_IPSR_GPSR(IP4_11_8, VI4_CLKENB),
864 PINMUX_IPSR_GPSR(IP4_11_8, DU_DG3),
865
866 PINMUX_IPSR_GPSR(IP4_15_12, CS0_N),
867 PINMUX_IPSR_GPSR(IP4_15_12, VI5_CLKENB),
868
869 PINMUX_IPSR_GPSR(IP4_19_16, CS1_N_A26),
870 PINMUX_IPSR_GPSR(IP4_19_16, VI5_CLK),
871 PINMUX_IPSR_MSEL(IP4_19_16, EX_WAIT0_B, SEL_LBSC_1),
872
873 PINMUX_IPSR_GPSR(IP4_23_20, BS_N),
874 PINMUX_IPSR_GPSR(IP4_23_20, QSTVA_QVS),
875 PINMUX_IPSR_MSEL(IP4_23_20, MSIOF3_SCK_D, SEL_MSIOF3_3),
876 PINMUX_IPSR_GPSR(IP4_23_20, SCK3),
877 PINMUX_IPSR_GPSR(IP4_23_20, HSCK3),
878 PINMUX_IPSR_GPSR(IP4_23_20, CAN1_TX),
879 PINMUX_IPSR_GPSR(IP4_23_20, CANFD1_TX),
880 PINMUX_IPSR_MSEL(IP4_23_20, IETX_A, SEL_IEBUS_0),
881
882 PINMUX_IPSR_GPSR(IP4_27_24, RD_N),
883 PINMUX_IPSR_MSEL(IP4_27_24, MSIOF3_SYNC_D, SEL_MSIOF3_3),
884 PINMUX_IPSR_MSEL(IP4_27_24, RX3_A, SEL_SCIF3_0),
885 PINMUX_IPSR_MSEL(IP4_27_24, HRX3_A, SEL_HSCIF3_0),
886 PINMUX_IPSR_MSEL(IP4_27_24, CAN0_TX_A, SEL_RCAN0_0),
887 PINMUX_IPSR_MSEL(IP4_27_24, CANFD0_TX_A, SEL_CANFD0_0),
888
889 PINMUX_IPSR_GPSR(IP4_31_28, RD_WR_N),
890 PINMUX_IPSR_MSEL(IP4_31_28, MSIOF3_RXD_D, SEL_MSIOF3_3),
891 PINMUX_IPSR_MSEL(IP4_31_28, TX3_A, SEL_SCIF3_0),
892 PINMUX_IPSR_MSEL(IP4_31_28, HTX3_A, SEL_HSCIF3_0),
893 PINMUX_IPSR_MSEL(IP4_31_28, CAN0_RX_A, SEL_RCAN0_0),
894 PINMUX_IPSR_MSEL(IP4_31_28, CANFD0_RX_A, SEL_CANFD0_0),
895
896 /* IPSR5 */
897 PINMUX_IPSR_GPSR(IP5_3_0, WE0_N),
898 PINMUX_IPSR_MSEL(IP5_3_0, MSIOF3_TXD_D, SEL_MSIOF3_3),
899 PINMUX_IPSR_GPSR(IP5_3_0, CTS3_N),
900 PINMUX_IPSR_GPSR(IP5_3_0, HCTS3_N),
901 PINMUX_IPSR_MSEL(IP5_3_0, SCL6_B, SEL_I2C6_1),
902 PINMUX_IPSR_GPSR(IP5_3_0, CAN_CLK),
903 PINMUX_IPSR_MSEL(IP5_3_0, IECLK_A, SEL_IEBUS_0),
904
905 PINMUX_IPSR_GPSR(IP5_7_4, WE1_N),
906 PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3),
907 PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N),
908 PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N),
909 PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1),
910 PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX),
911 PINMUX_IPSR_GPSR(IP5_7_4, CANFD1_RX),
912 PINMUX_IPSR_MSEL(IP5_7_4, IERX_A, SEL_IEBUS_0),
913
914 PINMUX_IPSR_MSEL(IP5_11_8, EX_WAIT0_A, SEL_LBSC_0),
915 PINMUX_IPSR_GPSR(IP5_11_8, QCLK),
916 PINMUX_IPSR_GPSR(IP5_11_8, VI4_CLK),
917 PINMUX_IPSR_GPSR(IP5_11_8, DU_DOTCLKOUT0),
918
919 PINMUX_IPSR_GPSR(IP5_15_12, D0),
920 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF2_SS1_B, SEL_MSIOF2_1),
921 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF3_SCK_A, SEL_MSIOF3_0),
922 PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA16),
923 PINMUX_IPSR_GPSR(IP5_15_12, VI5_DATA0),
924
925 PINMUX_IPSR_GPSR(IP5_19_16, D1),
926 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF2_SS2_B, SEL_MSIOF2_1),
927 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF3_SYNC_A, SEL_MSIOF3_0),
928 PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA17),
929 PINMUX_IPSR_GPSR(IP5_19_16, VI5_DATA1),
930
931 PINMUX_IPSR_GPSR(IP5_23_20, D2),
932 PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_RXD_A, SEL_MSIOF3_0),
933 PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA18),
934 PINMUX_IPSR_GPSR(IP5_23_20, VI5_DATA2),
935
936 PINMUX_IPSR_GPSR(IP5_27_24, D3),
937 PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0),
938 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA19),
939 PINMUX_IPSR_GPSR(IP5_27_24, VI5_DATA3),
940
941 PINMUX_IPSR_GPSR(IP5_31_28, D4),
942 PINMUX_IPSR_MSEL(IP5_31_28, MSIOF2_SCK_B, SEL_MSIOF2_1),
943 PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA20),
944 PINMUX_IPSR_GPSR(IP5_31_28, VI5_DATA4),
945
946 /* IPSR6 */
947 PINMUX_IPSR_GPSR(IP6_3_0, D5),
948 PINMUX_IPSR_MSEL(IP6_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1),
949 PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA21),
950 PINMUX_IPSR_GPSR(IP6_3_0, VI5_DATA5),
951
952 PINMUX_IPSR_GPSR(IP6_7_4, D6),
953 PINMUX_IPSR_MSEL(IP6_7_4, MSIOF2_RXD_B, SEL_MSIOF2_1),
954 PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA22),
955 PINMUX_IPSR_GPSR(IP6_7_4, VI5_DATA6),
956
957 PINMUX_IPSR_GPSR(IP6_11_8, D7),
958 PINMUX_IPSR_MSEL(IP6_11_8, MSIOF2_TXD_B, SEL_MSIOF2_1),
959 PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA23),
960 PINMUX_IPSR_GPSR(IP6_11_8, VI5_DATA7),
961
962 PINMUX_IPSR_GPSR(IP6_15_12, D8),
963 PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT0),
964 PINMUX_IPSR_MSEL(IP6_15_12, MSIOF2_SCK_D, SEL_MSIOF2_3),
965 PINMUX_IPSR_MSEL(IP6_15_12, SCK4_C, SEL_SCIF4_2),
966 PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA0_A, SEL_VIN4_0),
967 PINMUX_IPSR_GPSR(IP6_15_12, DU_DR0),
968
969 PINMUX_IPSR_GPSR(IP6_19_16, D9),
970 PINMUX_IPSR_GPSR(IP6_19_16, LCDOUT1),
971 PINMUX_IPSR_MSEL(IP6_19_16, MSIOF2_SYNC_D, SEL_MSIOF2_3),
972 PINMUX_IPSR_MSEL(IP6_19_16, VI4_DATA1_A, SEL_VIN4_0),
973 PINMUX_IPSR_GPSR(IP6_19_16, DU_DR1),
974
975 PINMUX_IPSR_GPSR(IP6_23_20, D10),
976 PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT2),
977 PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_RXD_D, SEL_MSIOF2_3),
978 PINMUX_IPSR_MSEL(IP6_23_20, HRX3_B, SEL_HSCIF3_1),
979 PINMUX_IPSR_MSEL(IP6_23_20, VI4_DATA2_A, SEL_VIN4_0),
980 PINMUX_IPSR_MSEL(IP6_23_20, CTS4_N_C, SEL_SCIF4_2),
981 PINMUX_IPSR_GPSR(IP6_23_20, DU_DR2),
982
983 PINMUX_IPSR_GPSR(IP6_27_24, D11),
984 PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT3),
985 PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3),
986 PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1),
987 PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0),
988 PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_C, SEL_SCIF4_2),
989 PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3),
990
991 PINMUX_IPSR_GPSR(IP6_31_28, D12),
992 PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT4),
993 PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_SS1_D, SEL_MSIOF2_3),
994 PINMUX_IPSR_MSEL(IP6_31_28, RX4_C, SEL_SCIF4_2),
995 PINMUX_IPSR_MSEL(IP6_31_28, VI4_DATA4_A, SEL_VIN4_0),
996 PINMUX_IPSR_GPSR(IP6_31_28, DU_DR4),
997
998 /* IPSR7 */
999 PINMUX_IPSR_GPSR(IP7_3_0, D13),
1000 PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT5),
1001 PINMUX_IPSR_MSEL(IP7_3_0, MSIOF2_SS2_D, SEL_MSIOF2_3),
1002 PINMUX_IPSR_MSEL(IP7_3_0, TX4_C, SEL_SCIF4_2),
1003 PINMUX_IPSR_MSEL(IP7_3_0, VI4_DATA5_A, SEL_VIN4_0),
1004 PINMUX_IPSR_GPSR(IP7_3_0, DU_DR5),
1005
1006 PINMUX_IPSR_GPSR(IP7_7_4, D14),
1007 PINMUX_IPSR_GPSR(IP7_7_4, LCDOUT6),
1008 PINMUX_IPSR_MSEL(IP7_7_4, MSIOF3_SS1_A, SEL_MSIOF3_0),
1009 PINMUX_IPSR_MSEL(IP7_7_4, HRX3_C, SEL_HSCIF3_2),
1010 PINMUX_IPSR_MSEL(IP7_7_4, VI4_DATA6_A, SEL_VIN4_0),
1011 PINMUX_IPSR_GPSR(IP7_7_4, DU_DR6),
1012 PINMUX_IPSR_MSEL(IP7_7_4, SCL6_C, SEL_I2C6_2),
1013
1014 PINMUX_IPSR_GPSR(IP7_11_8, D15),
1015 PINMUX_IPSR_GPSR(IP7_11_8, LCDOUT7),
1016 PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SS2_A, SEL_MSIOF3_0),
1017 PINMUX_IPSR_MSEL(IP7_11_8, HTX3_C, SEL_HSCIF3_2),
1018 PINMUX_IPSR_MSEL(IP7_11_8, VI4_DATA7_A, SEL_VIN4_0),
1019 PINMUX_IPSR_GPSR(IP7_11_8, DU_DR7),
1020 PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2),
1021
1022 PINMUX_IPSR_GPSR(IP7_15_12, FSCLKST),
1023
1024 PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK),
1025 PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4),
1026 PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1),
1027
1028 PINMUX_IPSR_GPSR(IP7_23_20, SD0_CMD),
1029 PINMUX_IPSR_MSEL(IP7_23_20, MSIOF1_SYNC_E, SEL_MSIOF1_4),
1030 PINMUX_IPSR_MSEL(IP7_23_20, STP_IVCXO27_0_B, SEL_SSP1_0_1),
1031
1032 PINMUX_IPSR_GPSR(IP7_27_24, SD0_DAT0),
1033 PINMUX_IPSR_MSEL(IP7_27_24, MSIOF1_RXD_E, SEL_MSIOF1_4),
1034 PINMUX_IPSR_MSEL(IP7_27_24, TS_SCK0_B, SEL_TSIF0_1),
1035 PINMUX_IPSR_MSEL(IP7_27_24, STP_ISCLK_0_B, SEL_SSP1_0_1),
1036
1037 PINMUX_IPSR_GPSR(IP7_31_28, SD0_DAT1),
1038 PINMUX_IPSR_MSEL(IP7_31_28, MSIOF1_TXD_E, SEL_MSIOF1_4),
1039 PINMUX_IPSR_MSEL(IP7_31_28, TS_SPSYNC0_B, SEL_TSIF0_1),
1040 PINMUX_IPSR_MSEL(IP7_31_28, STP_ISSYNC_0_B, SEL_SSP1_0_1),
1041
1042 /* IPSR8 */
1043 PINMUX_IPSR_GPSR(IP8_3_0, SD0_DAT2),
1044 PINMUX_IPSR_MSEL(IP8_3_0, MSIOF1_SS1_E, SEL_MSIOF1_4),
1045 PINMUX_IPSR_MSEL(IP8_3_0, TS_SDAT0_B, SEL_TSIF0_1),
1046 PINMUX_IPSR_MSEL(IP8_3_0, STP_ISD_0_B, SEL_SSP1_0_1),
1047
1048 PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT3),
1049 PINMUX_IPSR_MSEL(IP8_7_4, MSIOF1_SS2_E, SEL_MSIOF1_4),
1050 PINMUX_IPSR_MSEL(IP8_7_4, TS_SDEN0_B, SEL_TSIF0_1),
1051 PINMUX_IPSR_MSEL(IP8_7_4, STP_ISEN_0_B, SEL_SSP1_0_1),
1052
1053 PINMUX_IPSR_GPSR(IP8_11_8, SD1_CLK),
1054 PINMUX_IPSR_MSEL(IP8_11_8, MSIOF1_SCK_G, SEL_MSIOF1_6),
1055 PINMUX_IPSR_MSEL(IP8_11_8, SIM0_CLK_A, SEL_SIMCARD_0),
1056
1057 PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD),
1058 PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6),
1059 PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0),
1060 PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1),
1061
1062 PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0),
1063 PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4),
1064 PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6),
1065 PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1),
1066 PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1),
1067
1068 PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1),
1069 PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5),
1070 PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6),
1071 PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1),
1072 PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1),
1073
1074 PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2),
1075 PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6),
1076 PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6),
1077 PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1),
1078 PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1),
1079
1080 PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3),
1081 PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7),
1082 PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6),
1083 PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1),
1084 PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1),
1085
1086 /* IPSR9 */
1087 PINMUX_IPSR_GPSR(IP9_3_0, SD2_CLK),
1088
1089 PINMUX_IPSR_GPSR(IP9_7_4, SD2_DAT0),
1090
1091 PINMUX_IPSR_GPSR(IP9_11_8, SD2_DAT1),
1092
1093 PINMUX_IPSR_GPSR(IP9_15_12, SD2_DAT2),
1094
1095 PINMUX_IPSR_GPSR(IP9_19_16, SD2_DAT3),
1096
1097 PINMUX_IPSR_GPSR(IP9_23_20, SD2_DS),
1098 PINMUX_IPSR_MSEL(IP9_23_20, SATA_DEVSLP_B, SEL_SATA_1),
1099
1100 PINMUX_IPSR_GPSR(IP9_27_24, SD3_DAT4),
1101 PINMUX_IPSR_MSEL(IP9_27_24, SD2_CD_A, SEL_SDHI2_0),
1102
1103 PINMUX_IPSR_GPSR(IP9_31_28, SD3_DAT5),
1104 PINMUX_IPSR_MSEL(IP9_31_28, SD2_WP_A, SEL_SDHI2_0),
1105
1106 /* IPSR10 */
1107 PINMUX_IPSR_GPSR(IP10_3_0, SD3_DAT6),
1108 PINMUX_IPSR_GPSR(IP10_3_0, SD3_CD),
1109
1110 PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT7),
1111 PINMUX_IPSR_GPSR(IP10_7_4, SD3_WP),
1112
1113 PINMUX_IPSR_GPSR(IP10_11_8, SD0_CD),
1114 PINMUX_IPSR_MSEL(IP10_11_8, SCL2_B, SEL_I2C2_1),
1115 PINMUX_IPSR_MSEL(IP10_11_8, SIM0_RST_A, SEL_SIMCARD_0),
1116
1117 PINMUX_IPSR_GPSR(IP10_15_12, SD0_WP),
1118 PINMUX_IPSR_MSEL(IP10_15_12, SDA2_B, SEL_I2C2_1),
1119
1120 PINMUX_IPSR_MSEL(IP10_19_16, SD1_CD, I2C_SEL_0_0),
1121 PINMUX_IPSR_PHYS_MSEL(IP10_19_16, SIM0_CLK_B, I2C_SEL_0_0, SEL_SIMCARD_1),
1122 PINMUX_IPSR_PHYS(IP10_19_16, SCL0, I2C_SEL_0_1),
1123
1124 PINMUX_IPSR_MSEL(IP10_23_20, SD1_WP, I2C_SEL_0_0),
1125 PINMUX_IPSR_PHYS_MSEL(IP10_23_20, SIM0_D_B, I2C_SEL_0_0, SEL_SIMCARD_1),
1126 PINMUX_IPSR_PHYS(IP10_23_20, SDA0, I2C_SEL_0_1),
1127
1128 PINMUX_IPSR_GPSR(IP10_27_24, SCK0),
1129 PINMUX_IPSR_MSEL(IP10_27_24, HSCK1_B, SEL_HSCIF1_1),
1130 PINMUX_IPSR_MSEL(IP10_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1),
1131 PINMUX_IPSR_MSEL(IP10_27_24, AUDIO_CLKC_B, SEL_ADG_1),
1132 PINMUX_IPSR_MSEL(IP10_27_24, SDA2_A, SEL_I2C2_0),
1133 PINMUX_IPSR_MSEL(IP10_27_24, SIM0_RST_B, SEL_SIMCARD_1),
1134 PINMUX_IPSR_MSEL(IP10_27_24, STP_OPWM_0_C, SEL_SSP1_0_2),
1135 PINMUX_IPSR_MSEL(IP10_27_24, RIF0_CLK_B, SEL_DRIF0_1),
1136 PINMUX_IPSR_GPSR(IP10_27_24, ADICHS2),
1137
1138 PINMUX_IPSR_GPSR(IP10_31_28, RX0),
1139 PINMUX_IPSR_MSEL(IP10_31_28, HRX1_B, SEL_HSCIF1_1),
1140 PINMUX_IPSR_MSEL(IP10_31_28, TS_SCK0_C, SEL_TSIF0_2),
1141 PINMUX_IPSR_MSEL(IP10_31_28, STP_ISCLK_0_C, SEL_SSP1_0_2),
1142 PINMUX_IPSR_MSEL(IP10_31_28, RIF0_D0_B, SEL_DRIF0_1),
1143
1144 /* IPSR11 */
1145 PINMUX_IPSR_GPSR(IP11_3_0, TX0),
1146 PINMUX_IPSR_MSEL(IP11_3_0, HTX1_B, SEL_HSCIF1_1),
1147 PINMUX_IPSR_MSEL(IP11_3_0, TS_SPSYNC0_C, SEL_TSIF0_2),
1148 PINMUX_IPSR_MSEL(IP11_3_0, STP_ISSYNC_0_C, SEL_SSP1_0_2),
1149 PINMUX_IPSR_MSEL(IP11_3_0, RIF0_D1_B, SEL_DRIF0_1),
1150
1151 PINMUX_IPSR_GPSR(IP11_7_4, CTS0_N),
1152 PINMUX_IPSR_MSEL(IP11_7_4, HCTS1_N_B, SEL_HSCIF1_1),
1153 PINMUX_IPSR_MSEL(IP11_7_4, MSIOF1_SYNC_B, SEL_MSIOF1_1),
1154 PINMUX_IPSR_MSEL(IP11_7_4, TS_SPSYNC1_C, SEL_TSIF1_2),
1155 PINMUX_IPSR_MSEL(IP11_7_4, STP_ISSYNC_1_C, SEL_SSP1_1_2),
1156 PINMUX_IPSR_MSEL(IP11_7_4, RIF1_SYNC_B, SEL_DRIF1_1),
1157 PINMUX_IPSR_MSEL(IP11_7_4, AUDIO_CLKOUT_C, SEL_ADG_2),
1158 PINMUX_IPSR_GPSR(IP11_7_4, ADICS_SAMP),
1159
1160 PINMUX_IPSR_GPSR(IP11_11_8, RTS0_N),
1161 PINMUX_IPSR_MSEL(IP11_11_8, HRTS1_N_B, SEL_HSCIF1_1),
1162 PINMUX_IPSR_MSEL(IP11_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1),
1163 PINMUX_IPSR_MSEL(IP11_11_8, AUDIO_CLKA_B, SEL_ADG_1),
1164 PINMUX_IPSR_MSEL(IP11_11_8, SCL2_A, SEL_I2C2_0),
1165 PINMUX_IPSR_MSEL(IP11_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2),
1166 PINMUX_IPSR_MSEL(IP11_11_8, RIF0_SYNC_B, SEL_DRIF0_1),
1167 PINMUX_IPSR_GPSR(IP11_11_8, ADICHS1),
1168
1169 PINMUX_IPSR_MSEL(IP11_15_12, RX1_A, SEL_SCIF1_0),
1170 PINMUX_IPSR_MSEL(IP11_15_12, HRX1_A, SEL_HSCIF1_0),
1171 PINMUX_IPSR_MSEL(IP11_15_12, TS_SDAT0_C, SEL_TSIF0_2),
1172 PINMUX_IPSR_MSEL(IP11_15_12, STP_ISD_0_C, SEL_SSP1_0_2),
1173 PINMUX_IPSR_MSEL(IP11_15_12, RIF1_CLK_C, SEL_DRIF1_2),
1174
1175 PINMUX_IPSR_MSEL(IP11_19_16, TX1_A, SEL_SCIF1_0),
1176 PINMUX_IPSR_MSEL(IP11_19_16, HTX1_A, SEL_HSCIF1_0),
1177 PINMUX_IPSR_MSEL(IP11_19_16, TS_SDEN0_C, SEL_TSIF0_2),
1178 PINMUX_IPSR_MSEL(IP11_19_16, STP_ISEN_0_C, SEL_SSP1_0_2),
1179 PINMUX_IPSR_MSEL(IP11_19_16, RIF1_D0_C, SEL_DRIF1_2),
1180
1181 PINMUX_IPSR_GPSR(IP11_23_20, CTS1_N),
1182 PINMUX_IPSR_MSEL(IP11_23_20, HCTS1_N_A, SEL_HSCIF1_0),
1183 PINMUX_IPSR_MSEL(IP11_23_20, MSIOF1_RXD_B, SEL_MSIOF1_1),
1184 PINMUX_IPSR_MSEL(IP11_23_20, TS_SDEN1_C, SEL_TSIF1_2),
1185 PINMUX_IPSR_MSEL(IP11_23_20, STP_ISEN_1_C, SEL_SSP1_1_2),
1186 PINMUX_IPSR_MSEL(IP11_23_20, RIF1_D0_B, SEL_DRIF1_1),
1187 PINMUX_IPSR_GPSR(IP11_23_20, ADIDATA),
1188
1189 PINMUX_IPSR_GPSR(IP11_27_24, RTS1_N),
1190 PINMUX_IPSR_MSEL(IP11_27_24, HRTS1_N_A, SEL_HSCIF1_0),
1191 PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1),
1192 PINMUX_IPSR_MSEL(IP11_27_24, TS_SDAT1_C, SEL_TSIF1_2),
1193 PINMUX_IPSR_MSEL(IP11_27_24, STP_ISD_1_C, SEL_SSP1_1_2),
1194 PINMUX_IPSR_MSEL(IP11_27_24, RIF1_D1_B, SEL_DRIF1_1),
1195 PINMUX_IPSR_GPSR(IP11_27_24, ADICHS0),
1196
1197 PINMUX_IPSR_GPSR(IP11_31_28, SCK2),
1198 PINMUX_IPSR_MSEL(IP11_31_28, SCIF_CLK_B, SEL_SCIF1_1),
1199 PINMUX_IPSR_MSEL(IP11_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1),
1200 PINMUX_IPSR_MSEL(IP11_31_28, TS_SCK1_C, SEL_TSIF1_2),
1201 PINMUX_IPSR_MSEL(IP11_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2),
1202 PINMUX_IPSR_MSEL(IP11_31_28, RIF1_CLK_B, SEL_DRIF1_1),
1203 PINMUX_IPSR_GPSR(IP11_31_28, ADICLK),
1204
1205 /* IPSR12 */
1206 PINMUX_IPSR_MSEL(IP12_3_0, TX2_A, SEL_SCIF2_0),
1207 PINMUX_IPSR_MSEL(IP12_3_0, SD2_CD_B, SEL_SDHI2_1),
1208 PINMUX_IPSR_MSEL(IP12_3_0, SCL1_A, SEL_I2C1_0),
1209 PINMUX_IPSR_MSEL(IP12_3_0, FMCLK_A, SEL_FM_0),
1210 PINMUX_IPSR_MSEL(IP12_3_0, RIF1_D1_C, SEL_DRIF1_2),
1211 PINMUX_IPSR_MSEL(IP12_3_0, FSO_CFE_0_B, SEL_FSO_1),
1212
1213 PINMUX_IPSR_MSEL(IP12_7_4, RX2_A, SEL_SCIF2_0),
1214 PINMUX_IPSR_MSEL(IP12_7_4, SD2_WP_B, SEL_SDHI2_1),
1215 PINMUX_IPSR_MSEL(IP12_7_4, SDA1_A, SEL_I2C1_0),
1216 PINMUX_IPSR_MSEL(IP12_7_4, FMIN_A, SEL_FM_0),
1217 PINMUX_IPSR_MSEL(IP12_7_4, RIF1_SYNC_C, SEL_DRIF1_2),
1218 PINMUX_IPSR_MSEL(IP12_7_4, FSO_CFE_1_B, SEL_FSO_1),
1219
1220 PINMUX_IPSR_GPSR(IP12_11_8, HSCK0),
1221 PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3),
1222 PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKB_A, SEL_ADG_0),
1223 PINMUX_IPSR_MSEL(IP12_11_8, SSI_SDATA1_B, SEL_SSI_1),
1224 PINMUX_IPSR_MSEL(IP12_11_8, TS_SCK0_D, SEL_TSIF0_3),
1225 PINMUX_IPSR_MSEL(IP12_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3),
1226 PINMUX_IPSR_MSEL(IP12_11_8, RIF0_CLK_C, SEL_DRIF0_2),
1227
1228 PINMUX_IPSR_GPSR(IP12_15_12, HRX0),
1229 PINMUX_IPSR_MSEL(IP12_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3),
1230 PINMUX_IPSR_MSEL(IP12_15_12, SSI_SDATA2_B, SEL_SSI_1),
1231 PINMUX_IPSR_MSEL(IP12_15_12, TS_SDEN0_D, SEL_TSIF0_3),
1232 PINMUX_IPSR_MSEL(IP12_15_12, STP_ISEN_0_D, SEL_SSP1_0_3),
1233 PINMUX_IPSR_MSEL(IP12_15_12, RIF0_D0_C, SEL_DRIF0_2),
1234
1235 PINMUX_IPSR_GPSR(IP12_19_16, HTX0),
1236 PINMUX_IPSR_MSEL(IP12_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3),
1237 PINMUX_IPSR_MSEL(IP12_19_16, SSI_SDATA9_B, SEL_SSI_1),
1238 PINMUX_IPSR_MSEL(IP12_19_16, TS_SDAT0_D, SEL_TSIF0_3),
1239 PINMUX_IPSR_MSEL(IP12_19_16, STP_ISD_0_D, SEL_SSP1_0_3),
1240 PINMUX_IPSR_MSEL(IP12_19_16, RIF0_D1_C, SEL_DRIF0_2),
1241
1242 PINMUX_IPSR_GPSR(IP12_23_20, HCTS0_N),
1243 PINMUX_IPSR_MSEL(IP12_23_20, RX2_B, SEL_SCIF2_1),
1244 PINMUX_IPSR_MSEL(IP12_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3),
1245 PINMUX_IPSR_MSEL(IP12_23_20, SSI_SCK9_A, SEL_SSI_0),
1246 PINMUX_IPSR_MSEL(IP12_23_20, TS_SPSYNC0_D, SEL_TSIF0_3),
1247 PINMUX_IPSR_MSEL(IP12_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3),
1248 PINMUX_IPSR_MSEL(IP12_23_20, RIF0_SYNC_C, SEL_DRIF0_2),
1249 PINMUX_IPSR_MSEL(IP12_23_20, AUDIO_CLKOUT1_A, SEL_ADG_0),
1250
1251 PINMUX_IPSR_GPSR(IP12_27_24, HRTS0_N),
1252 PINMUX_IPSR_MSEL(IP12_27_24, TX2_B, SEL_SCIF2_1),
1253 PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3),
1254 PINMUX_IPSR_MSEL(IP12_27_24, SSI_WS9_A, SEL_SSI_0),
1255 PINMUX_IPSR_MSEL(IP12_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3),
1256 PINMUX_IPSR_MSEL(IP12_27_24, BPFCLK_A, SEL_FM_0),
1257 PINMUX_IPSR_MSEL(IP12_27_24, AUDIO_CLKOUT2_A, SEL_ADG_0),
1258
1259 PINMUX_IPSR_GPSR(IP12_31_28, MSIOF0_SYNC),
1260 PINMUX_IPSR_MSEL(IP12_31_28, AUDIO_CLKOUT_A, SEL_ADG_0),
1261
1262 /* IPSR13 */
1263 PINMUX_IPSR_GPSR(IP13_3_0, MSIOF0_SS1),
1264 PINMUX_IPSR_GPSR(IP13_3_0, RX5),
1265 PINMUX_IPSR_MSEL(IP13_3_0, AUDIO_CLKA_C, SEL_ADG_2),
1266 PINMUX_IPSR_MSEL(IP13_3_0, SSI_SCK2_A, SEL_SSI_0),
1267 PINMUX_IPSR_MSEL(IP13_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
1268 PINMUX_IPSR_MSEL(IP13_3_0, AUDIO_CLKOUT3_A, SEL_ADG_0),
1269 PINMUX_IPSR_MSEL(IP13_3_0, TCLK1_B, SEL_TIMER_TMU_1),
1270
1271 PINMUX_IPSR_GPSR(IP13_7_4, MSIOF0_SS2),
1272 PINMUX_IPSR_GPSR(IP13_7_4, TX5),
1273 PINMUX_IPSR_MSEL(IP13_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3),
1274 PINMUX_IPSR_MSEL(IP13_7_4, AUDIO_CLKC_A, SEL_ADG_0),
1275 PINMUX_IPSR_MSEL(IP13_7_4, SSI_WS2_A, SEL_SSI_0),
1276 PINMUX_IPSR_MSEL(IP13_7_4, STP_OPWM_0_D, SEL_SSP1_0_3),
1277 PINMUX_IPSR_MSEL(IP13_7_4, AUDIO_CLKOUT_D, SEL_ADG_3),
1278 PINMUX_IPSR_MSEL(IP13_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1),
1279
1280 PINMUX_IPSR_GPSR(IP13_11_8, MLB_CLK),
1281 PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_F, SEL_MSIOF1_5),
1282 PINMUX_IPSR_MSEL(IP13_11_8, SCL1_B, SEL_I2C1_1),
1283
1284 PINMUX_IPSR_GPSR(IP13_15_12, MLB_SIG),
1285 PINMUX_IPSR_MSEL(IP13_15_12, RX1_B, SEL_SCIF1_1),
1286 PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_SYNC_F, SEL_MSIOF1_5),
1287 PINMUX_IPSR_MSEL(IP13_15_12, SDA1_B, SEL_I2C1_1),
1288
1289 PINMUX_IPSR_GPSR(IP13_19_16, MLB_DAT),
1290 PINMUX_IPSR_MSEL(IP13_19_16, TX1_B, SEL_SCIF1_1),
1291 PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_RXD_F, SEL_MSIOF1_5),
1292
1293 PINMUX_IPSR_GPSR(IP13_23_20, SSI_SCK01239),
1294 PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_TXD_F, SEL_MSIOF1_5),
1295
1296 PINMUX_IPSR_GPSR(IP13_27_24, SSI_WS01239),
1297 PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_F, SEL_MSIOF1_5),
1298
1299 PINMUX_IPSR_GPSR(IP13_31_28, SSI_SDATA0),
1300 PINMUX_IPSR_MSEL(IP13_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5),
1301
1302 /* IPSR14 */
1303 PINMUX_IPSR_MSEL(IP14_3_0, SSI_SDATA1_A, SEL_SSI_0),
1304
1305 PINMUX_IPSR_MSEL(IP14_7_4, SSI_SDATA2_A, SEL_SSI_0),
1306 PINMUX_IPSR_MSEL(IP14_7_4, SSI_SCK1_B, SEL_SSI_1),
1307
1308 PINMUX_IPSR_GPSR(IP14_11_8, SSI_SCK349),
1309 PINMUX_IPSR_MSEL(IP14_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0),
1310 PINMUX_IPSR_MSEL(IP14_11_8, STP_OPWM_0_A, SEL_SSP1_0_0),
1311
1312 PINMUX_IPSR_GPSR(IP14_15_12, SSI_WS349),
1313 PINMUX_IPSR_MSEL(IP14_15_12, HCTS2_N_A, SEL_HSCIF2_0),
1314 PINMUX_IPSR_MSEL(IP14_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0),
1315 PINMUX_IPSR_MSEL(IP14_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0),
1316
1317 PINMUX_IPSR_GPSR(IP14_19_16, SSI_SDATA3),
1318 PINMUX_IPSR_MSEL(IP14_19_16, HRTS2_N_A, SEL_HSCIF2_0),
1319 PINMUX_IPSR_MSEL(IP14_19_16, MSIOF1_TXD_A, SEL_MSIOF1_0),
1320 PINMUX_IPSR_MSEL(IP14_19_16, TS_SCK0_A, SEL_TSIF0_0),
1321 PINMUX_IPSR_MSEL(IP14_19_16, STP_ISCLK_0_A, SEL_SSP1_0_0),
1322 PINMUX_IPSR_MSEL(IP14_19_16, RIF0_D1_A, SEL_DRIF0_0),
1323 PINMUX_IPSR_MSEL(IP14_19_16, RIF2_D0_A, SEL_DRIF2_0),
1324
1325 PINMUX_IPSR_GPSR(IP14_23_20, SSI_SCK4),
1326 PINMUX_IPSR_MSEL(IP14_23_20, HRX2_A, SEL_HSCIF2_0),
1327 PINMUX_IPSR_MSEL(IP14_23_20, MSIOF1_SCK_A, SEL_MSIOF1_0),
1328 PINMUX_IPSR_MSEL(IP14_23_20, TS_SDAT0_A, SEL_TSIF0_0),
1329 PINMUX_IPSR_MSEL(IP14_23_20, STP_ISD_0_A, SEL_SSP1_0_0),
1330 PINMUX_IPSR_MSEL(IP14_23_20, RIF0_CLK_A, SEL_DRIF0_0),
1331 PINMUX_IPSR_MSEL(IP14_23_20, RIF2_CLK_A, SEL_DRIF2_0),
1332
1333 PINMUX_IPSR_GPSR(IP14_27_24, SSI_WS4),
1334 PINMUX_IPSR_MSEL(IP14_27_24, HTX2_A, SEL_HSCIF2_0),
1335 PINMUX_IPSR_MSEL(IP14_27_24, MSIOF1_SYNC_A, SEL_MSIOF1_0),
1336 PINMUX_IPSR_MSEL(IP14_27_24, TS_SDEN0_A, SEL_TSIF0_0),
1337 PINMUX_IPSR_MSEL(IP14_27_24, STP_ISEN_0_A, SEL_SSP1_0_0),
1338 PINMUX_IPSR_MSEL(IP14_27_24, RIF0_SYNC_A, SEL_DRIF0_0),
1339 PINMUX_IPSR_MSEL(IP14_27_24, RIF2_SYNC_A, SEL_DRIF2_0),
1340
1341 PINMUX_IPSR_GPSR(IP14_31_28, SSI_SDATA4),
1342 PINMUX_IPSR_MSEL(IP14_31_28, HSCK2_A, SEL_HSCIF2_0),
1343 PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_RXD_A, SEL_MSIOF1_0),
1344 PINMUX_IPSR_MSEL(IP14_31_28, TS_SPSYNC0_A, SEL_TSIF0_0),
1345 PINMUX_IPSR_MSEL(IP14_31_28, STP_ISSYNC_0_A, SEL_SSP1_0_0),
1346 PINMUX_IPSR_MSEL(IP14_31_28, RIF0_D0_A, SEL_DRIF0_0),
1347 PINMUX_IPSR_MSEL(IP14_31_28, RIF2_D1_A, SEL_DRIF2_0),
1348
1349 /* IPSR15 */
1350 PINMUX_IPSR_GPSR(IP15_3_0, SSI_SCK6),
1351 PINMUX_IPSR_GPSR(IP15_3_0, USB2_PWEN),
1352 PINMUX_IPSR_MSEL(IP15_3_0, SIM0_RST_D, SEL_SIMCARD_3),
1353
1354 PINMUX_IPSR_GPSR(IP15_7_4, SSI_WS6),
1355 PINMUX_IPSR_GPSR(IP15_7_4, USB2_OVC),
1356 PINMUX_IPSR_MSEL(IP15_7_4, SIM0_D_D, SEL_SIMCARD_3),
1357
1358 PINMUX_IPSR_GPSR(IP15_11_8, SSI_SDATA6),
1359 PINMUX_IPSR_MSEL(IP15_11_8, SIM0_CLK_D, SEL_SIMCARD_3),
1360 PINMUX_IPSR_MSEL(IP15_11_8, SATA_DEVSLP_A, SEL_SATA_0),
1361
1362 PINMUX_IPSR_GPSR(IP15_15_12, SSI_SCK78),
1363 PINMUX_IPSR_MSEL(IP15_15_12, HRX2_B, SEL_HSCIF2_1),
1364 PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SCK_C, SEL_MSIOF1_2),
1365 PINMUX_IPSR_MSEL(IP15_15_12, TS_SCK1_A, SEL_TSIF1_0),
1366 PINMUX_IPSR_MSEL(IP15_15_12, STP_ISCLK_1_A, SEL_SSP1_1_0),
1367 PINMUX_IPSR_MSEL(IP15_15_12, RIF1_CLK_A, SEL_DRIF1_0),
1368 PINMUX_IPSR_MSEL(IP15_15_12, RIF3_CLK_A, SEL_DRIF3_0),
1369
1370 PINMUX_IPSR_GPSR(IP15_19_16, SSI_WS78),
1371 PINMUX_IPSR_MSEL(IP15_19_16, HTX2_B, SEL_HSCIF2_1),
1372 PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_SYNC_C, SEL_MSIOF1_2),
1373 PINMUX_IPSR_MSEL(IP15_19_16, TS_SDAT1_A, SEL_TSIF1_0),
1374 PINMUX_IPSR_MSEL(IP15_19_16, STP_ISD_1_A, SEL_SSP1_1_0),
1375 PINMUX_IPSR_MSEL(IP15_19_16, RIF1_SYNC_A, SEL_DRIF1_0),
1376 PINMUX_IPSR_MSEL(IP15_19_16, RIF3_SYNC_A, SEL_DRIF3_0),
1377
1378 PINMUX_IPSR_GPSR(IP15_23_20, SSI_SDATA7),
1379 PINMUX_IPSR_MSEL(IP15_23_20, HCTS2_N_B, SEL_HSCIF2_1),
1380 PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_RXD_C, SEL_MSIOF1_2),
1381 PINMUX_IPSR_MSEL(IP15_23_20, TS_SDEN1_A, SEL_TSIF1_0),
1382 PINMUX_IPSR_MSEL(IP15_23_20, STP_ISEN_1_A, SEL_SSP1_1_0),
1383 PINMUX_IPSR_MSEL(IP15_23_20, RIF1_D0_A, SEL_DRIF1_0),
1384 PINMUX_IPSR_MSEL(IP15_23_20, RIF3_D0_A, SEL_DRIF3_0),
1385 PINMUX_IPSR_MSEL(IP15_23_20, TCLK2_A, SEL_TIMER_TMU_0),
1386
1387 PINMUX_IPSR_GPSR(IP15_27_24, SSI_SDATA8),
1388 PINMUX_IPSR_MSEL(IP15_27_24, HRTS2_N_B, SEL_HSCIF2_1),
1389 PINMUX_IPSR_MSEL(IP15_27_24, MSIOF1_TXD_C, SEL_MSIOF1_2),
1390 PINMUX_IPSR_MSEL(IP15_27_24, TS_SPSYNC1_A, SEL_TSIF1_0),
1391 PINMUX_IPSR_MSEL(IP15_27_24, STP_ISSYNC_1_A, SEL_SSP1_1_0),
1392 PINMUX_IPSR_MSEL(IP15_27_24, RIF1_D1_A, SEL_DRIF1_0),
1393 PINMUX_IPSR_MSEL(IP15_27_24, RIF3_D1_A, SEL_DRIF3_0),
1394
1395 PINMUX_IPSR_MSEL(IP15_31_28, SSI_SDATA9_A, SEL_SSI_0),
1396 PINMUX_IPSR_MSEL(IP15_31_28, HSCK2_B, SEL_HSCIF2_1),
1397 PINMUX_IPSR_MSEL(IP15_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2),
1398 PINMUX_IPSR_MSEL(IP15_31_28, HSCK1_A, SEL_HSCIF1_0),
1399 PINMUX_IPSR_MSEL(IP15_31_28, SSI_WS1_B, SEL_SSI_1),
1400 PINMUX_IPSR_GPSR(IP15_31_28, SCK1),
1401 PINMUX_IPSR_MSEL(IP15_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0),
1402 PINMUX_IPSR_GPSR(IP15_31_28, SCK5),
1403
1404 /* IPSR16 */
1405 PINMUX_IPSR_MSEL(IP16_3_0, AUDIO_CLKA_A, SEL_ADG_0),
1406
1407 PINMUX_IPSR_MSEL(IP16_7_4, AUDIO_CLKB_B, SEL_ADG_1),
1408 PINMUX_IPSR_MSEL(IP16_7_4, SCIF_CLK_A, SEL_SCIF1_0),
1409 PINMUX_IPSR_MSEL(IP16_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3),
1410 PINMUX_IPSR_MSEL(IP16_7_4, REMOCON_A, SEL_REMOCON_0),
1411 PINMUX_IPSR_MSEL(IP16_7_4, TCLK1_A, SEL_TIMER_TMU_0),
1412
1413 PINMUX_IPSR_GPSR(IP16_11_8, USB0_PWEN),
1414 PINMUX_IPSR_MSEL(IP16_11_8, SIM0_RST_C, SEL_SIMCARD_2),
1415 PINMUX_IPSR_MSEL(IP16_11_8, TS_SCK1_D, SEL_TSIF1_3),
1416 PINMUX_IPSR_MSEL(IP16_11_8, STP_ISCLK_1_D, SEL_SSP1_1_3),
1417 PINMUX_IPSR_MSEL(IP16_11_8, BPFCLK_B, SEL_FM_1),
1418 PINMUX_IPSR_MSEL(IP16_11_8, RIF3_CLK_B, SEL_DRIF3_1),
1419
1420 PINMUX_IPSR_GPSR(IP16_15_12, USB0_OVC),
1421 PINMUX_IPSR_MSEL(IP16_11_8, SIM0_D_C, SEL_SIMCARD_2),
1422 PINMUX_IPSR_MSEL(IP16_11_8, TS_SDAT1_D, SEL_TSIF1_3),
1423 PINMUX_IPSR_MSEL(IP16_11_8, STP_ISD_1_D, SEL_SSP1_1_3),
1424 PINMUX_IPSR_MSEL(IP16_11_8, RIF3_SYNC_B, SEL_DRIF3_1),
1425
1426 PINMUX_IPSR_GPSR(IP16_19_16, USB1_PWEN),
1427 PINMUX_IPSR_MSEL(IP16_19_16, SIM0_CLK_C, SEL_SIMCARD_2),
1428 PINMUX_IPSR_MSEL(IP16_19_16, SSI_SCK1_A, SEL_SSI_0),
1429 PINMUX_IPSR_MSEL(IP16_19_16, TS_SCK0_E, SEL_TSIF0_4),
1430 PINMUX_IPSR_MSEL(IP16_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4),
1431 PINMUX_IPSR_MSEL(IP16_19_16, FMCLK_B, SEL_FM_1),
1432 PINMUX_IPSR_MSEL(IP16_19_16, RIF2_CLK_B, SEL_DRIF2_1),
1433 PINMUX_IPSR_MSEL(IP16_19_16, SPEEDIN_A, SEL_SPEED_PULSE_0),
1434
1435 PINMUX_IPSR_GPSR(IP16_23_20, USB1_OVC),
1436 PINMUX_IPSR_MSEL(IP16_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2),
1437 PINMUX_IPSR_MSEL(IP16_23_20, SSI_WS1_A, SEL_SSI_0),
1438 PINMUX_IPSR_MSEL(IP16_23_20, TS_SDAT0_E, SEL_TSIF0_4),
1439 PINMUX_IPSR_MSEL(IP16_23_20, STP_ISD_0_E, SEL_SSP1_0_4),
1440 PINMUX_IPSR_MSEL(IP16_23_20, FMIN_B, SEL_FM_1),
1441 PINMUX_IPSR_MSEL(IP16_23_20, RIF2_SYNC_B, SEL_DRIF2_1),
1442 PINMUX_IPSR_MSEL(IP16_23_20, REMOCON_B, SEL_REMOCON_1),
1443
1444 PINMUX_IPSR_GPSR(IP16_27_24, USB30_PWEN),
1445 PINMUX_IPSR_MSEL(IP16_27_24, AUDIO_CLKOUT_B, SEL_ADG_1),
1446 PINMUX_IPSR_MSEL(IP16_27_24, SSI_SCK2_B, SEL_SSI_1),
1447 PINMUX_IPSR_MSEL(IP16_27_24, TS_SDEN1_D, SEL_TSIF1_3),
1448 PINMUX_IPSR_MSEL(IP16_27_24, STP_ISEN_1_D, SEL_SSP1_1_3),
1449 PINMUX_IPSR_MSEL(IP16_27_24, STP_OPWM_0_E, SEL_SSP1_0_4),
1450 PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D0_B, SEL_DRIF3_1),
1451 PINMUX_IPSR_MSEL(IP16_27_24, TCLK2_B, SEL_TIMER_TMU_1),
1452 PINMUX_IPSR_GPSR(IP16_27_24, TPU0TO0),
1453
1454 PINMUX_IPSR_GPSR(IP16_31_28, USB30_OVC),
1455 PINMUX_IPSR_MSEL(IP16_31_28, AUDIO_CLKOUT1_B, SEL_ADG_1),
1456 PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS2_B, SEL_SSI_1),
1457 PINMUX_IPSR_MSEL(IP16_31_28, TS_SPSYNC1_D, SEL_TSIF1_3),
1458 PINMUX_IPSR_MSEL(IP16_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3),
1459 PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4),
1460 PINMUX_IPSR_MSEL(IP16_31_28, RIF3_D1_B, SEL_DRIF3_1),
1461 PINMUX_IPSR_MSEL(IP16_31_28, FSO_TOE_B, SEL_FSO_1),
1462 PINMUX_IPSR_GPSR(IP16_31_28, TPU0TO1),
1463
1464 /* IPSR17 */
1465 PINMUX_IPSR_GPSR(IP17_3_0, USB31_PWEN),
1466 PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKOUT2_B, SEL_ADG_1),
1467 PINMUX_IPSR_MSEL(IP17_3_0, SSI_SCK9_B, SEL_SSI_1),
1468 PINMUX_IPSR_MSEL(IP17_3_0, TS_SDEN0_E, SEL_TSIF0_4),
1469 PINMUX_IPSR_MSEL(IP17_3_0, STP_ISEN_0_E, SEL_SSP1_0_4),
1470 PINMUX_IPSR_MSEL(IP17_3_0, RIF2_D0_B, SEL_DRIF2_1),
1471 PINMUX_IPSR_GPSR(IP17_3_0, TPU0TO2),
1472
1473 PINMUX_IPSR_GPSR(IP17_7_4, USB31_OVC),
1474 PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKOUT3_B, SEL_ADG_1),
1475 PINMUX_IPSR_MSEL(IP17_7_4, SSI_WS9_B, SEL_SSI_1),
1476 PINMUX_IPSR_MSEL(IP17_7_4, TS_SPSYNC0_E, SEL_TSIF0_4),
1477 PINMUX_IPSR_MSEL(IP17_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4),
1478 PINMUX_IPSR_MSEL(IP17_7_4, RIF2_D1_B, SEL_DRIF2_1),
1479 PINMUX_IPSR_GPSR(IP17_7_4, TPU0TO3),
1480
1481 /*
1482 * Static pins can not be muxed between different functions but
1483 * still need mark entries in the pinmux list. Add each static
1484 * pin to the list without an associated function. The sh-pfc
1485 * core will do the right thing and skip trying to mux the pin
1486 * while still applying configuration to it.
1487 */
1488 #define FM(x) PINMUX_DATA(x##_MARK, 0),
1489 PINMUX_STATIC
1490 #undef FM
1491 };
1492
1493 /*
1494 * Pins not associated with a GPIO port.
1495 */
1496 enum {
1497 GP_ASSIGN_LAST(),
1498 NOGP_ALL(),
1499 };
1500
1501 static const struct sh_pfc_pin pinmux_pins[] = {
1502 PINMUX_GPIO_GP_ALL(),
1503 PINMUX_NOGP_ALL(),
1504 };
1505
1506 /* - AUDIO CLOCK ------------------------------------------------------------ */
1507 static const unsigned int audio_clk_a_a_pins[] = {
1508 /* CLK A */
1509 RCAR_GP_PIN(6, 22),
1510 };
1511 static const unsigned int audio_clk_a_a_mux[] = {
1512 AUDIO_CLKA_A_MARK,
1513 };
1514 static const unsigned int audio_clk_a_b_pins[] = {
1515 /* CLK A */
1516 RCAR_GP_PIN(5, 4),
1517 };
1518 static const unsigned int audio_clk_a_b_mux[] = {
1519 AUDIO_CLKA_B_MARK,
1520 };
1521 static const unsigned int audio_clk_a_c_pins[] = {
1522 /* CLK A */
1523 RCAR_GP_PIN(5, 19),
1524 };
1525 static const unsigned int audio_clk_a_c_mux[] = {
1526 AUDIO_CLKA_C_MARK,
1527 };
1528 static const unsigned int audio_clk_b_a_pins[] = {
1529 /* CLK B */
1530 RCAR_GP_PIN(5, 12),
1531 };
1532 static const unsigned int audio_clk_b_a_mux[] = {
1533 AUDIO_CLKB_A_MARK,
1534 };
1535 static const unsigned int audio_clk_b_b_pins[] = {
1536 /* CLK B */
1537 RCAR_GP_PIN(6, 23),
1538 };
1539 static const unsigned int audio_clk_b_b_mux[] = {
1540 AUDIO_CLKB_B_MARK,
1541 };
1542 static const unsigned int audio_clk_c_a_pins[] = {
1543 /* CLK C */
1544 RCAR_GP_PIN(5, 21),
1545 };
1546 static const unsigned int audio_clk_c_a_mux[] = {
1547 AUDIO_CLKC_A_MARK,
1548 };
1549 static const unsigned int audio_clk_c_b_pins[] = {
1550 /* CLK C */
1551 RCAR_GP_PIN(5, 0),
1552 };
1553 static const unsigned int audio_clk_c_b_mux[] = {
1554 AUDIO_CLKC_B_MARK,
1555 };
1556 static const unsigned int audio_clkout_a_pins[] = {
1557 /* CLKOUT */
1558 RCAR_GP_PIN(5, 18),
1559 };
1560 static const unsigned int audio_clkout_a_mux[] = {
1561 AUDIO_CLKOUT_A_MARK,
1562 };
1563 static const unsigned int audio_clkout_b_pins[] = {
1564 /* CLKOUT */
1565 RCAR_GP_PIN(6, 28),
1566 };
1567 static const unsigned int audio_clkout_b_mux[] = {
1568 AUDIO_CLKOUT_B_MARK,
1569 };
1570 static const unsigned int audio_clkout_c_pins[] = {
1571 /* CLKOUT */
1572 RCAR_GP_PIN(5, 3),
1573 };
1574 static const unsigned int audio_clkout_c_mux[] = {
1575 AUDIO_CLKOUT_C_MARK,
1576 };
1577 static const unsigned int audio_clkout_d_pins[] = {
1578 /* CLKOUT */
1579 RCAR_GP_PIN(5, 21),
1580 };
1581 static const unsigned int audio_clkout_d_mux[] = {
1582 AUDIO_CLKOUT_D_MARK,
1583 };
1584 static const unsigned int audio_clkout1_a_pins[] = {
1585 /* CLKOUT1 */
1586 RCAR_GP_PIN(5, 15),
1587 };
1588 static const unsigned int audio_clkout1_a_mux[] = {
1589 AUDIO_CLKOUT1_A_MARK,
1590 };
1591 static const unsigned int audio_clkout1_b_pins[] = {
1592 /* CLKOUT1 */
1593 RCAR_GP_PIN(6, 29),
1594 };
1595 static const unsigned int audio_clkout1_b_mux[] = {
1596 AUDIO_CLKOUT1_B_MARK,
1597 };
1598 static const unsigned int audio_clkout2_a_pins[] = {
1599 /* CLKOUT2 */
1600 RCAR_GP_PIN(5, 16),
1601 };
1602 static const unsigned int audio_clkout2_a_mux[] = {
1603 AUDIO_CLKOUT2_A_MARK,
1604 };
1605 static const unsigned int audio_clkout2_b_pins[] = {
1606 /* CLKOUT2 */
1607 RCAR_GP_PIN(6, 30),
1608 };
1609 static const unsigned int audio_clkout2_b_mux[] = {
1610 AUDIO_CLKOUT2_B_MARK,
1611 };
1612
1613 static const unsigned int audio_clkout3_a_pins[] = {
1614 /* CLKOUT3 */
1615 RCAR_GP_PIN(5, 19),
1616 };
1617 static const unsigned int audio_clkout3_a_mux[] = {
1618 AUDIO_CLKOUT3_A_MARK,
1619 };
1620 static const unsigned int audio_clkout3_b_pins[] = {
1621 /* CLKOUT3 */
1622 RCAR_GP_PIN(6, 31),
1623 };
1624 static const unsigned int audio_clkout3_b_mux[] = {
1625 AUDIO_CLKOUT3_B_MARK,
1626 };
1627
1628 /* - EtherAVB --------------------------------------------------------------- */
1629 static const unsigned int avb_link_pins[] = {
1630 /* AVB_LINK */
1631 RCAR_GP_PIN(2, 12),
1632 };
1633 static const unsigned int avb_link_mux[] = {
1634 AVB_LINK_MARK,
1635 };
1636 static const unsigned int avb_magic_pins[] = {
1637 /* AVB_MAGIC_ */
1638 RCAR_GP_PIN(2, 10),
1639 };
1640 static const unsigned int avb_magic_mux[] = {
1641 AVB_MAGIC_MARK,
1642 };
1643 static const unsigned int avb_phy_int_pins[] = {
1644 /* AVB_PHY_INT */
1645 RCAR_GP_PIN(2, 11),
1646 };
1647 static const unsigned int avb_phy_int_mux[] = {
1648 AVB_PHY_INT_MARK,
1649 };
1650 static const unsigned int avb_mdio_pins[] = {
1651 /* AVB_MDC, AVB_MDIO */
1652 RCAR_GP_PIN(2, 9), PIN_AVB_MDIO,
1653 };
1654 static const unsigned int avb_mdio_mux[] = {
1655 AVB_MDC_MARK, AVB_MDIO_MARK,
1656 };
1657 static const unsigned int avb_mii_pins[] = {
1658 /*
1659 * AVB_TX_CTL, AVB_TXC, AVB_TD0,
1660 * AVB_TD1, AVB_TD2, AVB_TD3,
1661 * AVB_RX_CTL, AVB_RXC, AVB_RD0,
1662 * AVB_RD1, AVB_RD2, AVB_RD3,
1663 * AVB_TXCREFCLK
1664 */
1665 PIN_AVB_TX_CTL, PIN_AVB_TXC, PIN_AVB_TD0,
1666 PIN_AVB_TD1, PIN_AVB_TD2, PIN_AVB_TD3,
1667 PIN_AVB_RX_CTL, PIN_AVB_RXC, PIN_AVB_RD0,
1668 PIN_AVB_RD1, PIN_AVB_RD2, PIN_AVB_RD3,
1669 PIN_AVB_TXCREFCLK,
1670 };
1671 static const unsigned int avb_mii_mux[] = {
1672 AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,
1673 AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
1674 AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
1675 AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
1676 AVB_TXCREFCLK_MARK,
1677 };
1678 static const unsigned int avb_avtp_pps_pins[] = {
1679 /* AVB_AVTP_PPS */
1680 RCAR_GP_PIN(2, 6),
1681 };
1682 static const unsigned int avb_avtp_pps_mux[] = {
1683 AVB_AVTP_PPS_MARK,
1684 };
1685 static const unsigned int avb_avtp_match_a_pins[] = {
1686 /* AVB_AVTP_MATCH_A */
1687 RCAR_GP_PIN(2, 13),
1688 };
1689 static const unsigned int avb_avtp_match_a_mux[] = {
1690 AVB_AVTP_MATCH_A_MARK,
1691 };
1692 static const unsigned int avb_avtp_capture_a_pins[] = {
1693 /* AVB_AVTP_CAPTURE_A */
1694 RCAR_GP_PIN(2, 14),
1695 };
1696 static const unsigned int avb_avtp_capture_a_mux[] = {
1697 AVB_AVTP_CAPTURE_A_MARK,
1698 };
1699 static const unsigned int avb_avtp_match_b_pins[] = {
1700 /* AVB_AVTP_MATCH_B */
1701 RCAR_GP_PIN(1, 8),
1702 };
1703 static const unsigned int avb_avtp_match_b_mux[] = {
1704 AVB_AVTP_MATCH_B_MARK,
1705 };
1706 static const unsigned int avb_avtp_capture_b_pins[] = {
1707 /* AVB_AVTP_CAPTURE_B */
1708 RCAR_GP_PIN(1, 11),
1709 };
1710 static const unsigned int avb_avtp_capture_b_mux[] = {
1711 AVB_AVTP_CAPTURE_B_MARK,
1712 };
1713
1714 /* - CAN ------------------------------------------------------------------ */
1715 static const unsigned int can0_data_a_pins[] = {
1716 /* TX, RX */
1717 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1718 };
1719 static const unsigned int can0_data_a_mux[] = {
1720 CAN0_TX_A_MARK, CAN0_RX_A_MARK,
1721 };
1722 static const unsigned int can0_data_b_pins[] = {
1723 /* TX, RX */
1724 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1725 };
1726 static const unsigned int can0_data_b_mux[] = {
1727 CAN0_TX_B_MARK, CAN0_RX_B_MARK,
1728 };
1729 static const unsigned int can1_data_pins[] = {
1730 /* TX, RX */
1731 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
1732 };
1733 static const unsigned int can1_data_mux[] = {
1734 CAN1_TX_MARK, CAN1_RX_MARK,
1735 };
1736
1737 /* - CAN Clock -------------------------------------------------------------- */
1738 static const unsigned int can_clk_pins[] = {
1739 /* CLK */
1740 RCAR_GP_PIN(1, 25),
1741 };
1742 static const unsigned int can_clk_mux[] = {
1743 CAN_CLK_MARK,
1744 };
1745
1746 /* - CAN FD --------------------------------------------------------------- */
1747 static const unsigned int canfd0_data_a_pins[] = {
1748 /* TX, RX */
1749 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1750 };
1751 static const unsigned int canfd0_data_a_mux[] = {
1752 CANFD0_TX_A_MARK, CANFD0_RX_A_MARK,
1753 };
1754 static const unsigned int canfd0_data_b_pins[] = {
1755 /* TX, RX */
1756 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1757 };
1758 static const unsigned int canfd0_data_b_mux[] = {
1759 CANFD0_TX_B_MARK, CANFD0_RX_B_MARK,
1760 };
1761 static const unsigned int canfd1_data_pins[] = {
1762 /* TX, RX */
1763 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
1764 };
1765 static const unsigned int canfd1_data_mux[] = {
1766 CANFD1_TX_MARK, CANFD1_RX_MARK,
1767 };
1768
1769 /* - DRIF0 --------------------------------------------------------------- */
1770 static const unsigned int drif0_ctrl_a_pins[] = {
1771 /* CLK, SYNC */
1772 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1773 };
1774 static const unsigned int drif0_ctrl_a_mux[] = {
1775 RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,
1776 };
1777 static const unsigned int drif0_data0_a_pins[] = {
1778 /* D0 */
1779 RCAR_GP_PIN(6, 10),
1780 };
1781 static const unsigned int drif0_data0_a_mux[] = {
1782 RIF0_D0_A_MARK,
1783 };
1784 static const unsigned int drif0_data1_a_pins[] = {
1785 /* D1 */
1786 RCAR_GP_PIN(6, 7),
1787 };
1788 static const unsigned int drif0_data1_a_mux[] = {
1789 RIF0_D1_A_MARK,
1790 };
1791 static const unsigned int drif0_ctrl_b_pins[] = {
1792 /* CLK, SYNC */
1793 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
1794 };
1795 static const unsigned int drif0_ctrl_b_mux[] = {
1796 RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,
1797 };
1798 static const unsigned int drif0_data0_b_pins[] = {
1799 /* D0 */
1800 RCAR_GP_PIN(5, 1),
1801 };
1802 static const unsigned int drif0_data0_b_mux[] = {
1803 RIF0_D0_B_MARK,
1804 };
1805 static const unsigned int drif0_data1_b_pins[] = {
1806 /* D1 */
1807 RCAR_GP_PIN(5, 2),
1808 };
1809 static const unsigned int drif0_data1_b_mux[] = {
1810 RIF0_D1_B_MARK,
1811 };
1812 static const unsigned int drif0_ctrl_c_pins[] = {
1813 /* CLK, SYNC */
1814 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15),
1815 };
1816 static const unsigned int drif0_ctrl_c_mux[] = {
1817 RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK,
1818 };
1819 static const unsigned int drif0_data0_c_pins[] = {
1820 /* D0 */
1821 RCAR_GP_PIN(5, 13),
1822 };
1823 static const unsigned int drif0_data0_c_mux[] = {
1824 RIF0_D0_C_MARK,
1825 };
1826 static const unsigned int drif0_data1_c_pins[] = {
1827 /* D1 */
1828 RCAR_GP_PIN(5, 14),
1829 };
1830 static const unsigned int drif0_data1_c_mux[] = {
1831 RIF0_D1_C_MARK,
1832 };
1833 /* - DRIF1 --------------------------------------------------------------- */
1834 static const unsigned int drif1_ctrl_a_pins[] = {
1835 /* CLK, SYNC */
1836 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
1837 };
1838 static const unsigned int drif1_ctrl_a_mux[] = {
1839 RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK,
1840 };
1841 static const unsigned int drif1_data0_a_pins[] = {
1842 /* D0 */
1843 RCAR_GP_PIN(6, 19),
1844 };
1845 static const unsigned int drif1_data0_a_mux[] = {
1846 RIF1_D0_A_MARK,
1847 };
1848 static const unsigned int drif1_data1_a_pins[] = {
1849 /* D1 */
1850 RCAR_GP_PIN(6, 20),
1851 };
1852 static const unsigned int drif1_data1_a_mux[] = {
1853 RIF1_D1_A_MARK,
1854 };
1855 static const unsigned int drif1_ctrl_b_pins[] = {
1856 /* CLK, SYNC */
1857 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3),
1858 };
1859 static const unsigned int drif1_ctrl_b_mux[] = {
1860 RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK,
1861 };
1862 static const unsigned int drif1_data0_b_pins[] = {
1863 /* D0 */
1864 RCAR_GP_PIN(5, 7),
1865 };
1866 static const unsigned int drif1_data0_b_mux[] = {
1867 RIF1_D0_B_MARK,
1868 };
1869 static const unsigned int drif1_data1_b_pins[] = {
1870 /* D1 */
1871 RCAR_GP_PIN(5, 8),
1872 };
1873 static const unsigned int drif1_data1_b_mux[] = {
1874 RIF1_D1_B_MARK,
1875 };
1876 static const unsigned int drif1_ctrl_c_pins[] = {
1877 /* CLK, SYNC */
1878 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
1879 };
1880 static const unsigned int drif1_ctrl_c_mux[] = {
1881 RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK,
1882 };
1883 static const unsigned int drif1_data0_c_pins[] = {
1884 /* D0 */
1885 RCAR_GP_PIN(5, 6),
1886 };
1887 static const unsigned int drif1_data0_c_mux[] = {
1888 RIF1_D0_C_MARK,
1889 };
1890 static const unsigned int drif1_data1_c_pins[] = {
1891 /* D1 */
1892 RCAR_GP_PIN(5, 10),
1893 };
1894 static const unsigned int drif1_data1_c_mux[] = {
1895 RIF1_D1_C_MARK,
1896 };
1897 /* - DRIF2 --------------------------------------------------------------- */
1898 static const unsigned int drif2_ctrl_a_pins[] = {
1899 /* CLK, SYNC */
1900 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1901 };
1902 static const unsigned int drif2_ctrl_a_mux[] = {
1903 RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,
1904 };
1905 static const unsigned int drif2_data0_a_pins[] = {
1906 /* D0 */
1907 RCAR_GP_PIN(6, 7),
1908 };
1909 static const unsigned int drif2_data0_a_mux[] = {
1910 RIF2_D0_A_MARK,
1911 };
1912 static const unsigned int drif2_data1_a_pins[] = {
1913 /* D1 */
1914 RCAR_GP_PIN(6, 10),
1915 };
1916 static const unsigned int drif2_data1_a_mux[] = {
1917 RIF2_D1_A_MARK,
1918 };
1919 static const unsigned int drif2_ctrl_b_pins[] = {
1920 /* CLK, SYNC */
1921 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
1922 };
1923 static const unsigned int drif2_ctrl_b_mux[] = {
1924 RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,
1925 };
1926 static const unsigned int drif2_data0_b_pins[] = {
1927 /* D0 */
1928 RCAR_GP_PIN(6, 30),
1929 };
1930 static const unsigned int drif2_data0_b_mux[] = {
1931 RIF2_D0_B_MARK,
1932 };
1933 static const unsigned int drif2_data1_b_pins[] = {
1934 /* D1 */
1935 RCAR_GP_PIN(6, 31),
1936 };
1937 static const unsigned int drif2_data1_b_mux[] = {
1938 RIF2_D1_B_MARK,
1939 };
1940 /* - DRIF3 --------------------------------------------------------------- */
1941 static const unsigned int drif3_ctrl_a_pins[] = {
1942 /* CLK, SYNC */
1943 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
1944 };
1945 static const unsigned int drif3_ctrl_a_mux[] = {
1946 RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,
1947 };
1948 static const unsigned int drif3_data0_a_pins[] = {
1949 /* D0 */
1950 RCAR_GP_PIN(6, 19),
1951 };
1952 static const unsigned int drif3_data0_a_mux[] = {
1953 RIF3_D0_A_MARK,
1954 };
1955 static const unsigned int drif3_data1_a_pins[] = {
1956 /* D1 */
1957 RCAR_GP_PIN(6, 20),
1958 };
1959 static const unsigned int drif3_data1_a_mux[] = {
1960 RIF3_D1_A_MARK,
1961 };
1962 static const unsigned int drif3_ctrl_b_pins[] = {
1963 /* CLK, SYNC */
1964 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
1965 };
1966 static const unsigned int drif3_ctrl_b_mux[] = {
1967 RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,
1968 };
1969 static const unsigned int drif3_data0_b_pins[] = {
1970 /* D0 */
1971 RCAR_GP_PIN(6, 28),
1972 };
1973 static const unsigned int drif3_data0_b_mux[] = {
1974 RIF3_D0_B_MARK,
1975 };
1976 static const unsigned int drif3_data1_b_pins[] = {
1977 /* D1 */
1978 RCAR_GP_PIN(6, 29),
1979 };
1980 static const unsigned int drif3_data1_b_mux[] = {
1981 RIF3_D1_B_MARK,
1982 };
1983
1984 /* - DU --------------------------------------------------------------------- */
1985 static const unsigned int du_rgb666_pins[] = {
1986 /* R[7:2], G[7:2], B[7:2] */
1987 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
1988 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
1989 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
1990 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
1991 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
1992 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
1993 };
1994 static const unsigned int du_rgb666_mux[] = {
1995 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
1996 DU_DR3_MARK, DU_DR2_MARK,
1997 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
1998 DU_DG3_MARK, DU_DG2_MARK,
1999 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2000 DU_DB3_MARK, DU_DB2_MARK,
2001 };
2002 static const unsigned int du_rgb888_pins[] = {
2003 /* R[7:0], G[7:0], B[7:0] */
2004 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2005 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2006 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
2007 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2008 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2009 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
2010 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
2011 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
2012 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
2013 };
2014 static const unsigned int du_rgb888_mux[] = {
2015 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2016 DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
2017 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2018 DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
2019 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2020 DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
2021 };
2022 static const unsigned int du_clk_out_0_pins[] = {
2023 /* CLKOUT */
2024 RCAR_GP_PIN(1, 27),
2025 };
2026 static const unsigned int du_clk_out_0_mux[] = {
2027 DU_DOTCLKOUT0_MARK
2028 };
2029 static const unsigned int du_clk_out_1_pins[] = {
2030 /* CLKOUT */
2031 RCAR_GP_PIN(2, 3),
2032 };
2033 static const unsigned int du_clk_out_1_mux[] = {
2034 DU_DOTCLKOUT1_MARK
2035 };
2036 static const unsigned int du_sync_pins[] = {
2037 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
2038 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
2039 };
2040 static const unsigned int du_sync_mux[] = {
2041 DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
2042 };
2043 static const unsigned int du_oddf_pins[] = {
2044 /* EXDISP/EXODDF/EXCDE */
2045 RCAR_GP_PIN(2, 2),
2046 };
2047 static const unsigned int du_oddf_mux[] = {
2048 DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
2049 };
2050 static const unsigned int du_cde_pins[] = {
2051 /* CDE */
2052 RCAR_GP_PIN(2, 0),
2053 };
2054 static const unsigned int du_cde_mux[] = {
2055 DU_CDE_MARK,
2056 };
2057 static const unsigned int du_disp_pins[] = {
2058 /* DISP */
2059 RCAR_GP_PIN(2, 1),
2060 };
2061 static const unsigned int du_disp_mux[] = {
2062 DU_DISP_MARK,
2063 };
2064 /* - HSCIF0 ----------------------------------------------------------------- */
2065 static const unsigned int hscif0_data_pins[] = {
2066 /* RX, TX */
2067 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
2068 };
2069 static const unsigned int hscif0_data_mux[] = {
2070 HRX0_MARK, HTX0_MARK,
2071 };
2072 static const unsigned int hscif0_clk_pins[] = {
2073 /* SCK */
2074 RCAR_GP_PIN(5, 12),
2075 };
2076 static const unsigned int hscif0_clk_mux[] = {
2077 HSCK0_MARK,
2078 };
2079 static const unsigned int hscif0_ctrl_pins[] = {
2080 /* RTS, CTS */
2081 RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
2082 };
2083 static const unsigned int hscif0_ctrl_mux[] = {
2084 HRTS0_N_MARK, HCTS0_N_MARK,
2085 };
2086 /* - HSCIF1 ----------------------------------------------------------------- */
2087 static const unsigned int hscif1_data_a_pins[] = {
2088 /* RX, TX */
2089 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2090 };
2091 static const unsigned int hscif1_data_a_mux[] = {
2092 HRX1_A_MARK, HTX1_A_MARK,
2093 };
2094 static const unsigned int hscif1_clk_a_pins[] = {
2095 /* SCK */
2096 RCAR_GP_PIN(6, 21),
2097 };
2098 static const unsigned int hscif1_clk_a_mux[] = {
2099 HSCK1_A_MARK,
2100 };
2101 static const unsigned int hscif1_ctrl_a_pins[] = {
2102 /* RTS, CTS */
2103 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
2104 };
2105 static const unsigned int hscif1_ctrl_a_mux[] = {
2106 HRTS1_N_A_MARK, HCTS1_N_A_MARK,
2107 };
2108
2109 static const unsigned int hscif1_data_b_pins[] = {
2110 /* RX, TX */
2111 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2112 };
2113 static const unsigned int hscif1_data_b_mux[] = {
2114 HRX1_B_MARK, HTX1_B_MARK,
2115 };
2116 static const unsigned int hscif1_clk_b_pins[] = {
2117 /* SCK */
2118 RCAR_GP_PIN(5, 0),
2119 };
2120 static const unsigned int hscif1_clk_b_mux[] = {
2121 HSCK1_B_MARK,
2122 };
2123 static const unsigned int hscif1_ctrl_b_pins[] = {
2124 /* RTS, CTS */
2125 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
2126 };
2127 static const unsigned int hscif1_ctrl_b_mux[] = {
2128 HRTS1_N_B_MARK, HCTS1_N_B_MARK,
2129 };
2130 /* - HSCIF2 ----------------------------------------------------------------- */
2131 static const unsigned int hscif2_data_a_pins[] = {
2132 /* RX, TX */
2133 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
2134 };
2135 static const unsigned int hscif2_data_a_mux[] = {
2136 HRX2_A_MARK, HTX2_A_MARK,
2137 };
2138 static const unsigned int hscif2_clk_a_pins[] = {
2139 /* SCK */
2140 RCAR_GP_PIN(6, 10),
2141 };
2142 static const unsigned int hscif2_clk_a_mux[] = {
2143 HSCK2_A_MARK,
2144 };
2145 static const unsigned int hscif2_ctrl_a_pins[] = {
2146 /* RTS, CTS */
2147 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
2148 };
2149 static const unsigned int hscif2_ctrl_a_mux[] = {
2150 HRTS2_N_A_MARK, HCTS2_N_A_MARK,
2151 };
2152
2153 static const unsigned int hscif2_data_b_pins[] = {
2154 /* RX, TX */
2155 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2156 };
2157 static const unsigned int hscif2_data_b_mux[] = {
2158 HRX2_B_MARK, HTX2_B_MARK,
2159 };
2160 static const unsigned int hscif2_clk_b_pins[] = {
2161 /* SCK */
2162 RCAR_GP_PIN(6, 21),
2163 };
2164 static const unsigned int hscif2_clk_b_mux[] = {
2165 HSCK2_B_MARK,
2166 };
2167 static const unsigned int hscif2_ctrl_b_pins[] = {
2168 /* RTS, CTS */
2169 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19),
2170 };
2171 static const unsigned int hscif2_ctrl_b_mux[] = {
2172 HRTS2_N_B_MARK, HCTS2_N_B_MARK,
2173 };
2174 /* - HSCIF3 ----------------------------------------------------------------- */
2175 static const unsigned int hscif3_data_a_pins[] = {
2176 /* RX, TX */
2177 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
2178 };
2179 static const unsigned int hscif3_data_a_mux[] = {
2180 HRX3_A_MARK, HTX3_A_MARK,
2181 };
2182 static const unsigned int hscif3_clk_pins[] = {
2183 /* SCK */
2184 RCAR_GP_PIN(1, 22),
2185 };
2186 static const unsigned int hscif3_clk_mux[] = {
2187 HSCK3_MARK,
2188 };
2189 static const unsigned int hscif3_ctrl_pins[] = {
2190 /* RTS, CTS */
2191 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2192 };
2193 static const unsigned int hscif3_ctrl_mux[] = {
2194 HRTS3_N_MARK, HCTS3_N_MARK,
2195 };
2196
2197 static const unsigned int hscif3_data_b_pins[] = {
2198 /* RX, TX */
2199 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
2200 };
2201 static const unsigned int hscif3_data_b_mux[] = {
2202 HRX3_B_MARK, HTX3_B_MARK,
2203 };
2204 static const unsigned int hscif3_data_c_pins[] = {
2205 /* RX, TX */
2206 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2207 };
2208 static const unsigned int hscif3_data_c_mux[] = {
2209 HRX3_C_MARK, HTX3_C_MARK,
2210 };
2211 static const unsigned int hscif3_data_d_pins[] = {
2212 /* RX, TX */
2213 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2214 };
2215 static const unsigned int hscif3_data_d_mux[] = {
2216 HRX3_D_MARK, HTX3_D_MARK,
2217 };
2218 /* - HSCIF4 ----------------------------------------------------------------- */
2219 static const unsigned int hscif4_data_a_pins[] = {
2220 /* RX, TX */
2221 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
2222 };
2223 static const unsigned int hscif4_data_a_mux[] = {
2224 HRX4_A_MARK, HTX4_A_MARK,
2225 };
2226 static const unsigned int hscif4_clk_pins[] = {
2227 /* SCK */
2228 RCAR_GP_PIN(1, 11),
2229 };
2230 static const unsigned int hscif4_clk_mux[] = {
2231 HSCK4_MARK,
2232 };
2233 static const unsigned int hscif4_ctrl_pins[] = {
2234 /* RTS, CTS */
2235 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
2236 };
2237 static const unsigned int hscif4_ctrl_mux[] = {
2238 HRTS4_N_MARK, HCTS4_N_MARK,
2239 };
2240
2241 static const unsigned int hscif4_data_b_pins[] = {
2242 /* RX, TX */
2243 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2244 };
2245 static const unsigned int hscif4_data_b_mux[] = {
2246 HRX4_B_MARK, HTX4_B_MARK,
2247 };
2248
2249 /* - I2C -------------------------------------------------------------------- */
2250 static const unsigned int i2c0_pins[] = {
2251 /* SCL, SDA */
2252 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
2253 };
2254
2255 static const unsigned int i2c0_mux[] = {
2256 SCL0_MARK, SDA0_MARK,
2257 };
2258
2259 static const unsigned int i2c1_a_pins[] = {
2260 /* SDA, SCL */
2261 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
2262 };
2263 static const unsigned int i2c1_a_mux[] = {
2264 SDA1_A_MARK, SCL1_A_MARK,
2265 };
2266 static const unsigned int i2c1_b_pins[] = {
2267 /* SDA, SCL */
2268 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
2269 };
2270 static const unsigned int i2c1_b_mux[] = {
2271 SDA1_B_MARK, SCL1_B_MARK,
2272 };
2273 static const unsigned int i2c2_a_pins[] = {
2274 /* SDA, SCL */
2275 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
2276 };
2277 static const unsigned int i2c2_a_mux[] = {
2278 SDA2_A_MARK, SCL2_A_MARK,
2279 };
2280 static const unsigned int i2c2_b_pins[] = {
2281 /* SDA, SCL */
2282 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
2283 };
2284 static const unsigned int i2c2_b_mux[] = {
2285 SDA2_B_MARK, SCL2_B_MARK,
2286 };
2287
2288 static const unsigned int i2c3_pins[] = {
2289 /* SCL, SDA */
2290 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2291 };
2292
2293 static const unsigned int i2c3_mux[] = {
2294 SCL3_MARK, SDA3_MARK,
2295 };
2296
2297 static const unsigned int i2c5_pins[] = {
2298 /* SCL, SDA */
2299 RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
2300 };
2301
2302 static const unsigned int i2c5_mux[] = {
2303 SCL5_MARK, SDA5_MARK,
2304 };
2305
2306 static const unsigned int i2c6_a_pins[] = {
2307 /* SDA, SCL */
2308 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2309 };
2310 static const unsigned int i2c6_a_mux[] = {
2311 SDA6_A_MARK, SCL6_A_MARK,
2312 };
2313 static const unsigned int i2c6_b_pins[] = {
2314 /* SDA, SCL */
2315 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2316 };
2317 static const unsigned int i2c6_b_mux[] = {
2318 SDA6_B_MARK, SCL6_B_MARK,
2319 };
2320 static const unsigned int i2c6_c_pins[] = {
2321 /* SDA, SCL */
2322 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
2323 };
2324 static const unsigned int i2c6_c_mux[] = {
2325 SDA6_C_MARK, SCL6_C_MARK,
2326 };
2327
2328 /* - INTC-EX ---------------------------------------------------------------- */
2329 static const unsigned int intc_ex_irq0_pins[] = {
2330 /* IRQ0 */
2331 RCAR_GP_PIN(2, 0),
2332 };
2333 static const unsigned int intc_ex_irq0_mux[] = {
2334 IRQ0_MARK,
2335 };
2336 static const unsigned int intc_ex_irq1_pins[] = {
2337 /* IRQ1 */
2338 RCAR_GP_PIN(2, 1),
2339 };
2340 static const unsigned int intc_ex_irq1_mux[] = {
2341 IRQ1_MARK,
2342 };
2343 static const unsigned int intc_ex_irq2_pins[] = {
2344 /* IRQ2 */
2345 RCAR_GP_PIN(2, 2),
2346 };
2347 static const unsigned int intc_ex_irq2_mux[] = {
2348 IRQ2_MARK,
2349 };
2350 static const unsigned int intc_ex_irq3_pins[] = {
2351 /* IRQ3 */
2352 RCAR_GP_PIN(2, 3),
2353 };
2354 static const unsigned int intc_ex_irq3_mux[] = {
2355 IRQ3_MARK,
2356 };
2357 static const unsigned int intc_ex_irq4_pins[] = {
2358 /* IRQ4 */
2359 RCAR_GP_PIN(2, 4),
2360 };
2361 static const unsigned int intc_ex_irq4_mux[] = {
2362 IRQ4_MARK,
2363 };
2364 static const unsigned int intc_ex_irq5_pins[] = {
2365 /* IRQ5 */
2366 RCAR_GP_PIN(2, 5),
2367 };
2368 static const unsigned int intc_ex_irq5_mux[] = {
2369 IRQ5_MARK,
2370 };
2371
2372 /* - MLB+ ------------------------------------------------------------------- */
2373 static const unsigned int mlb_3pin_pins[] = {
2374 RCAR_GP_PIN(5, 23), RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
2375 };
2376 static const unsigned int mlb_3pin_mux[] = {
2377 MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK,
2378 };
2379
2380 /* - MSIOF0 ----------------------------------------------------------------- */
2381 static const unsigned int msiof0_clk_pins[] = {
2382 /* SCK */
2383 RCAR_GP_PIN(5, 17),
2384 };
2385 static const unsigned int msiof0_clk_mux[] = {
2386 MSIOF0_SCK_MARK,
2387 };
2388 static const unsigned int msiof0_sync_pins[] = {
2389 /* SYNC */
2390 RCAR_GP_PIN(5, 18),
2391 };
2392 static const unsigned int msiof0_sync_mux[] = {
2393 MSIOF0_SYNC_MARK,
2394 };
2395 static const unsigned int msiof0_ss1_pins[] = {
2396 /* SS1 */
2397 RCAR_GP_PIN(5, 19),
2398 };
2399 static const unsigned int msiof0_ss1_mux[] = {
2400 MSIOF0_SS1_MARK,
2401 };
2402 static const unsigned int msiof0_ss2_pins[] = {
2403 /* SS2 */
2404 RCAR_GP_PIN(5, 21),
2405 };
2406 static const unsigned int msiof0_ss2_mux[] = {
2407 MSIOF0_SS2_MARK,
2408 };
2409 static const unsigned int msiof0_txd_pins[] = {
2410 /* TXD */
2411 RCAR_GP_PIN(5, 20),
2412 };
2413 static const unsigned int msiof0_txd_mux[] = {
2414 MSIOF0_TXD_MARK,
2415 };
2416 static const unsigned int msiof0_rxd_pins[] = {
2417 /* RXD */
2418 RCAR_GP_PIN(5, 22),
2419 };
2420 static const unsigned int msiof0_rxd_mux[] = {
2421 MSIOF0_RXD_MARK,
2422 };
2423 /* - MSIOF1 ----------------------------------------------------------------- */
2424 static const unsigned int msiof1_clk_a_pins[] = {
2425 /* SCK */
2426 RCAR_GP_PIN(6, 8),
2427 };
2428 static const unsigned int msiof1_clk_a_mux[] = {
2429 MSIOF1_SCK_A_MARK,
2430 };
2431 static const unsigned int msiof1_sync_a_pins[] = {
2432 /* SYNC */
2433 RCAR_GP_PIN(6, 9),
2434 };
2435 static const unsigned int msiof1_sync_a_mux[] = {
2436 MSIOF1_SYNC_A_MARK,
2437 };
2438 static const unsigned int msiof1_ss1_a_pins[] = {
2439 /* SS1 */
2440 RCAR_GP_PIN(6, 5),
2441 };
2442 static const unsigned int msiof1_ss1_a_mux[] = {
2443 MSIOF1_SS1_A_MARK,
2444 };
2445 static const unsigned int msiof1_ss2_a_pins[] = {
2446 /* SS2 */
2447 RCAR_GP_PIN(6, 6),
2448 };
2449 static const unsigned int msiof1_ss2_a_mux[] = {
2450 MSIOF1_SS2_A_MARK,
2451 };
2452 static const unsigned int msiof1_txd_a_pins[] = {
2453 /* TXD */
2454 RCAR_GP_PIN(6, 7),
2455 };
2456 static const unsigned int msiof1_txd_a_mux[] = {
2457 MSIOF1_TXD_A_MARK,
2458 };
2459 static const unsigned int msiof1_rxd_a_pins[] = {
2460 /* RXD */
2461 RCAR_GP_PIN(6, 10),
2462 };
2463 static const unsigned int msiof1_rxd_a_mux[] = {
2464 MSIOF1_RXD_A_MARK,
2465 };
2466 static const unsigned int msiof1_clk_b_pins[] = {
2467 /* SCK */
2468 RCAR_GP_PIN(5, 9),
2469 };
2470 static const unsigned int msiof1_clk_b_mux[] = {
2471 MSIOF1_SCK_B_MARK,
2472 };
2473 static const unsigned int msiof1_sync_b_pins[] = {
2474 /* SYNC */
2475 RCAR_GP_PIN(5, 3),
2476 };
2477 static const unsigned int msiof1_sync_b_mux[] = {
2478 MSIOF1_SYNC_B_MARK,
2479 };
2480 static const unsigned int msiof1_ss1_b_pins[] = {
2481 /* SS1 */
2482 RCAR_GP_PIN(5, 4),
2483 };
2484 static const unsigned int msiof1_ss1_b_mux[] = {
2485 MSIOF1_SS1_B_MARK,
2486 };
2487 static const unsigned int msiof1_ss2_b_pins[] = {
2488 /* SS2 */
2489 RCAR_GP_PIN(5, 0),
2490 };
2491 static const unsigned int msiof1_ss2_b_mux[] = {
2492 MSIOF1_SS2_B_MARK,
2493 };
2494 static const unsigned int msiof1_txd_b_pins[] = {
2495 /* TXD */
2496 RCAR_GP_PIN(5, 8),
2497 };
2498 static const unsigned int msiof1_txd_b_mux[] = {
2499 MSIOF1_TXD_B_MARK,
2500 };
2501 static const unsigned int msiof1_rxd_b_pins[] = {
2502 /* RXD */
2503 RCAR_GP_PIN(5, 7),
2504 };
2505 static const unsigned int msiof1_rxd_b_mux[] = {
2506 MSIOF1_RXD_B_MARK,
2507 };
2508 static const unsigned int msiof1_clk_c_pins[] = {
2509 /* SCK */
2510 RCAR_GP_PIN(6, 17),
2511 };
2512 static const unsigned int msiof1_clk_c_mux[] = {
2513 MSIOF1_SCK_C_MARK,
2514 };
2515 static const unsigned int msiof1_sync_c_pins[] = {
2516 /* SYNC */
2517 RCAR_GP_PIN(6, 18),
2518 };
2519 static const unsigned int msiof1_sync_c_mux[] = {
2520 MSIOF1_SYNC_C_MARK,
2521 };
2522 static const unsigned int msiof1_ss1_c_pins[] = {
2523 /* SS1 */
2524 RCAR_GP_PIN(6, 21),
2525 };
2526 static const unsigned int msiof1_ss1_c_mux[] = {
2527 MSIOF1_SS1_C_MARK,
2528 };
2529 static const unsigned int msiof1_ss2_c_pins[] = {
2530 /* SS2 */
2531 RCAR_GP_PIN(6, 27),
2532 };
2533 static const unsigned int msiof1_ss2_c_mux[] = {
2534 MSIOF1_SS2_C_MARK,
2535 };
2536 static const unsigned int msiof1_txd_c_pins[] = {
2537 /* TXD */
2538 RCAR_GP_PIN(6, 20),
2539 };
2540 static const unsigned int msiof1_txd_c_mux[] = {
2541 MSIOF1_TXD_C_MARK,
2542 };
2543 static const unsigned int msiof1_rxd_c_pins[] = {
2544 /* RXD */
2545 RCAR_GP_PIN(6, 19),
2546 };
2547 static const unsigned int msiof1_rxd_c_mux[] = {
2548 MSIOF1_RXD_C_MARK,
2549 };
2550 static const unsigned int msiof1_clk_d_pins[] = {
2551 /* SCK */
2552 RCAR_GP_PIN(5, 12),
2553 };
2554 static const unsigned int msiof1_clk_d_mux[] = {
2555 MSIOF1_SCK_D_MARK,
2556 };
2557 static const unsigned int msiof1_sync_d_pins[] = {
2558 /* SYNC */
2559 RCAR_GP_PIN(5, 15),
2560 };
2561 static const unsigned int msiof1_sync_d_mux[] = {
2562 MSIOF1_SYNC_D_MARK,
2563 };
2564 static const unsigned int msiof1_ss1_d_pins[] = {
2565 /* SS1 */
2566 RCAR_GP_PIN(5, 16),
2567 };
2568 static const unsigned int msiof1_ss1_d_mux[] = {
2569 MSIOF1_SS1_D_MARK,
2570 };
2571 static const unsigned int msiof1_ss2_d_pins[] = {
2572 /* SS2 */
2573 RCAR_GP_PIN(5, 21),
2574 };
2575 static const unsigned int msiof1_ss2_d_mux[] = {
2576 MSIOF1_SS2_D_MARK,
2577 };
2578 static const unsigned int msiof1_txd_d_pins[] = {
2579 /* TXD */
2580 RCAR_GP_PIN(5, 14),
2581 };
2582 static const unsigned int msiof1_txd_d_mux[] = {
2583 MSIOF1_TXD_D_MARK,
2584 };
2585 static const unsigned int msiof1_rxd_d_pins[] = {
2586 /* RXD */
2587 RCAR_GP_PIN(5, 13),
2588 };
2589 static const unsigned int msiof1_rxd_d_mux[] = {
2590 MSIOF1_RXD_D_MARK,
2591 };
2592 static const unsigned int msiof1_clk_e_pins[] = {
2593 /* SCK */
2594 RCAR_GP_PIN(3, 0),
2595 };
2596 static const unsigned int msiof1_clk_e_mux[] = {
2597 MSIOF1_SCK_E_MARK,
2598 };
2599 static const unsigned int msiof1_sync_e_pins[] = {
2600 /* SYNC */
2601 RCAR_GP_PIN(3, 1),
2602 };
2603 static const unsigned int msiof1_sync_e_mux[] = {
2604 MSIOF1_SYNC_E_MARK,
2605 };
2606 static const unsigned int msiof1_ss1_e_pins[] = {
2607 /* SS1 */
2608 RCAR_GP_PIN(3, 4),
2609 };
2610 static const unsigned int msiof1_ss1_e_mux[] = {
2611 MSIOF1_SS1_E_MARK,
2612 };
2613 static const unsigned int msiof1_ss2_e_pins[] = {
2614 /* SS2 */
2615 RCAR_GP_PIN(3, 5),
2616 };
2617 static const unsigned int msiof1_ss2_e_mux[] = {
2618 MSIOF1_SS2_E_MARK,
2619 };
2620 static const unsigned int msiof1_txd_e_pins[] = {
2621 /* TXD */
2622 RCAR_GP_PIN(3, 3),
2623 };
2624 static const unsigned int msiof1_txd_e_mux[] = {
2625 MSIOF1_TXD_E_MARK,
2626 };
2627 static const unsigned int msiof1_rxd_e_pins[] = {
2628 /* RXD */
2629 RCAR_GP_PIN(3, 2),
2630 };
2631 static const unsigned int msiof1_rxd_e_mux[] = {
2632 MSIOF1_RXD_E_MARK,
2633 };
2634 static const unsigned int msiof1_clk_f_pins[] = {
2635 /* SCK */
2636 RCAR_GP_PIN(5, 23),
2637 };
2638 static const unsigned int msiof1_clk_f_mux[] = {
2639 MSIOF1_SCK_F_MARK,
2640 };
2641 static const unsigned int msiof1_sync_f_pins[] = {
2642 /* SYNC */
2643 RCAR_GP_PIN(5, 24),
2644 };
2645 static const unsigned int msiof1_sync_f_mux[] = {
2646 MSIOF1_SYNC_F_MARK,
2647 };
2648 static const unsigned int msiof1_ss1_f_pins[] = {
2649 /* SS1 */
2650 RCAR_GP_PIN(6, 1),
2651 };
2652 static const unsigned int msiof1_ss1_f_mux[] = {
2653 MSIOF1_SS1_F_MARK,
2654 };
2655 static const unsigned int msiof1_ss2_f_pins[] = {
2656 /* SS2 */
2657 RCAR_GP_PIN(6, 2),
2658 };
2659 static const unsigned int msiof1_ss2_f_mux[] = {
2660 MSIOF1_SS2_F_MARK,
2661 };
2662 static const unsigned int msiof1_txd_f_pins[] = {
2663 /* TXD */
2664 RCAR_GP_PIN(6, 0),
2665 };
2666 static const unsigned int msiof1_txd_f_mux[] = {
2667 MSIOF1_TXD_F_MARK,
2668 };
2669 static const unsigned int msiof1_rxd_f_pins[] = {
2670 /* RXD */
2671 RCAR_GP_PIN(5, 25),
2672 };
2673 static const unsigned int msiof1_rxd_f_mux[] = {
2674 MSIOF1_RXD_F_MARK,
2675 };
2676 static const unsigned int msiof1_clk_g_pins[] = {
2677 /* SCK */
2678 RCAR_GP_PIN(3, 6),
2679 };
2680 static const unsigned int msiof1_clk_g_mux[] = {
2681 MSIOF1_SCK_G_MARK,
2682 };
2683 static const unsigned int msiof1_sync_g_pins[] = {
2684 /* SYNC */
2685 RCAR_GP_PIN(3, 7),
2686 };
2687 static const unsigned int msiof1_sync_g_mux[] = {
2688 MSIOF1_SYNC_G_MARK,
2689 };
2690 static const unsigned int msiof1_ss1_g_pins[] = {
2691 /* SS1 */
2692 RCAR_GP_PIN(3, 10),
2693 };
2694 static const unsigned int msiof1_ss1_g_mux[] = {
2695 MSIOF1_SS1_G_MARK,
2696 };
2697 static const unsigned int msiof1_ss2_g_pins[] = {
2698 /* SS2 */
2699 RCAR_GP_PIN(3, 11),
2700 };
2701 static const unsigned int msiof1_ss2_g_mux[] = {
2702 MSIOF1_SS2_G_MARK,
2703 };
2704 static const unsigned int msiof1_txd_g_pins[] = {
2705 /* TXD */
2706 RCAR_GP_PIN(3, 9),
2707 };
2708 static const unsigned int msiof1_txd_g_mux[] = {
2709 MSIOF1_TXD_G_MARK,
2710 };
2711 static const unsigned int msiof1_rxd_g_pins[] = {
2712 /* RXD */
2713 RCAR_GP_PIN(3, 8),
2714 };
2715 static const unsigned int msiof1_rxd_g_mux[] = {
2716 MSIOF1_RXD_G_MARK,
2717 };
2718 /* - MSIOF2 ----------------------------------------------------------------- */
2719 static const unsigned int msiof2_clk_a_pins[] = {
2720 /* SCK */
2721 RCAR_GP_PIN(1, 9),
2722 };
2723 static const unsigned int msiof2_clk_a_mux[] = {
2724 MSIOF2_SCK_A_MARK,
2725 };
2726 static const unsigned int msiof2_sync_a_pins[] = {
2727 /* SYNC */
2728 RCAR_GP_PIN(1, 8),
2729 };
2730 static const unsigned int msiof2_sync_a_mux[] = {
2731 MSIOF2_SYNC_A_MARK,
2732 };
2733 static const unsigned int msiof2_ss1_a_pins[] = {
2734 /* SS1 */
2735 RCAR_GP_PIN(1, 6),
2736 };
2737 static const unsigned int msiof2_ss1_a_mux[] = {
2738 MSIOF2_SS1_A_MARK,
2739 };
2740 static const unsigned int msiof2_ss2_a_pins[] = {
2741 /* SS2 */
2742 RCAR_GP_PIN(1, 7),
2743 };
2744 static const unsigned int msiof2_ss2_a_mux[] = {
2745 MSIOF2_SS2_A_MARK,
2746 };
2747 static const unsigned int msiof2_txd_a_pins[] = {
2748 /* TXD */
2749 RCAR_GP_PIN(1, 11),
2750 };
2751 static const unsigned int msiof2_txd_a_mux[] = {
2752 MSIOF2_TXD_A_MARK,
2753 };
2754 static const unsigned int msiof2_rxd_a_pins[] = {
2755 /* RXD */
2756 RCAR_GP_PIN(1, 10),
2757 };
2758 static const unsigned int msiof2_rxd_a_mux[] = {
2759 MSIOF2_RXD_A_MARK,
2760 };
2761 static const unsigned int msiof2_clk_b_pins[] = {
2762 /* SCK */
2763 RCAR_GP_PIN(0, 4),
2764 };
2765 static const unsigned int msiof2_clk_b_mux[] = {
2766 MSIOF2_SCK_B_MARK,
2767 };
2768 static const unsigned int msiof2_sync_b_pins[] = {
2769 /* SYNC */
2770 RCAR_GP_PIN(0, 5),
2771 };
2772 static const unsigned int msiof2_sync_b_mux[] = {
2773 MSIOF2_SYNC_B_MARK,
2774 };
2775 static const unsigned int msiof2_ss1_b_pins[] = {
2776 /* SS1 */
2777 RCAR_GP_PIN(0, 0),
2778 };
2779 static const unsigned int msiof2_ss1_b_mux[] = {
2780 MSIOF2_SS1_B_MARK,
2781 };
2782 static const unsigned int msiof2_ss2_b_pins[] = {
2783 /* SS2 */
2784 RCAR_GP_PIN(0, 1),
2785 };
2786 static const unsigned int msiof2_ss2_b_mux[] = {
2787 MSIOF2_SS2_B_MARK,
2788 };
2789 static const unsigned int msiof2_txd_b_pins[] = {
2790 /* TXD */
2791 RCAR_GP_PIN(0, 7),
2792 };
2793 static const unsigned int msiof2_txd_b_mux[] = {
2794 MSIOF2_TXD_B_MARK,
2795 };
2796 static const unsigned int msiof2_rxd_b_pins[] = {
2797 /* RXD */
2798 RCAR_GP_PIN(0, 6),
2799 };
2800 static const unsigned int msiof2_rxd_b_mux[] = {
2801 MSIOF2_RXD_B_MARK,
2802 };
2803 static const unsigned int msiof2_clk_c_pins[] = {
2804 /* SCK */
2805 RCAR_GP_PIN(2, 12),
2806 };
2807 static const unsigned int msiof2_clk_c_mux[] = {
2808 MSIOF2_SCK_C_MARK,
2809 };
2810 static const unsigned int msiof2_sync_c_pins[] = {
2811 /* SYNC */
2812 RCAR_GP_PIN(2, 11),
2813 };
2814 static const unsigned int msiof2_sync_c_mux[] = {
2815 MSIOF2_SYNC_C_MARK,
2816 };
2817 static const unsigned int msiof2_ss1_c_pins[] = {
2818 /* SS1 */
2819 RCAR_GP_PIN(2, 10),
2820 };
2821 static const unsigned int msiof2_ss1_c_mux[] = {
2822 MSIOF2_SS1_C_MARK,
2823 };
2824 static const unsigned int msiof2_ss2_c_pins[] = {
2825 /* SS2 */
2826 RCAR_GP_PIN(2, 9),
2827 };
2828 static const unsigned int msiof2_ss2_c_mux[] = {
2829 MSIOF2_SS2_C_MARK,
2830 };
2831 static const unsigned int msiof2_txd_c_pins[] = {
2832 /* TXD */
2833 RCAR_GP_PIN(2, 14),
2834 };
2835 static const unsigned int msiof2_txd_c_mux[] = {
2836 MSIOF2_TXD_C_MARK,
2837 };
2838 static const unsigned int msiof2_rxd_c_pins[] = {
2839 /* RXD */
2840 RCAR_GP_PIN(2, 13),
2841 };
2842 static const unsigned int msiof2_rxd_c_mux[] = {
2843 MSIOF2_RXD_C_MARK,
2844 };
2845 static const unsigned int msiof2_clk_d_pins[] = {
2846 /* SCK */
2847 RCAR_GP_PIN(0, 8),
2848 };
2849 static const unsigned int msiof2_clk_d_mux[] = {
2850 MSIOF2_SCK_D_MARK,
2851 };
2852 static const unsigned int msiof2_sync_d_pins[] = {
2853 /* SYNC */
2854 RCAR_GP_PIN(0, 9),
2855 };
2856 static const unsigned int msiof2_sync_d_mux[] = {
2857 MSIOF2_SYNC_D_MARK,
2858 };
2859 static const unsigned int msiof2_ss1_d_pins[] = {
2860 /* SS1 */
2861 RCAR_GP_PIN(0, 12),
2862 };
2863 static const unsigned int msiof2_ss1_d_mux[] = {
2864 MSIOF2_SS1_D_MARK,
2865 };
2866 static const unsigned int msiof2_ss2_d_pins[] = {
2867 /* SS2 */
2868 RCAR_GP_PIN(0, 13),
2869 };
2870 static const unsigned int msiof2_ss2_d_mux[] = {
2871 MSIOF2_SS2_D_MARK,
2872 };
2873 static const unsigned int msiof2_txd_d_pins[] = {
2874 /* TXD */
2875 RCAR_GP_PIN(0, 11),
2876 };
2877 static const unsigned int msiof2_txd_d_mux[] = {
2878 MSIOF2_TXD_D_MARK,
2879 };
2880 static const unsigned int msiof2_rxd_d_pins[] = {
2881 /* RXD */
2882 RCAR_GP_PIN(0, 10),
2883 };
2884 static const unsigned int msiof2_rxd_d_mux[] = {
2885 MSIOF2_RXD_D_MARK,
2886 };
2887 /* - MSIOF3 ----------------------------------------------------------------- */
2888 static const unsigned int msiof3_clk_a_pins[] = {
2889 /* SCK */
2890 RCAR_GP_PIN(0, 0),
2891 };
2892 static const unsigned int msiof3_clk_a_mux[] = {
2893 MSIOF3_SCK_A_MARK,
2894 };
2895 static const unsigned int msiof3_sync_a_pins[] = {
2896 /* SYNC */
2897 RCAR_GP_PIN(0, 1),
2898 };
2899 static const unsigned int msiof3_sync_a_mux[] = {
2900 MSIOF3_SYNC_A_MARK,
2901 };
2902 static const unsigned int msiof3_ss1_a_pins[] = {
2903 /* SS1 */
2904 RCAR_GP_PIN(0, 14),
2905 };
2906 static const unsigned int msiof3_ss1_a_mux[] = {
2907 MSIOF3_SS1_A_MARK,
2908 };
2909 static const unsigned int msiof3_ss2_a_pins[] = {
2910 /* SS2 */
2911 RCAR_GP_PIN(0, 15),
2912 };
2913 static const unsigned int msiof3_ss2_a_mux[] = {
2914 MSIOF3_SS2_A_MARK,
2915 };
2916 static const unsigned int msiof3_txd_a_pins[] = {
2917 /* TXD */
2918 RCAR_GP_PIN(0, 3),
2919 };
2920 static const unsigned int msiof3_txd_a_mux[] = {
2921 MSIOF3_TXD_A_MARK,
2922 };
2923 static const unsigned int msiof3_rxd_a_pins[] = {
2924 /* RXD */
2925 RCAR_GP_PIN(0, 2),
2926 };
2927 static const unsigned int msiof3_rxd_a_mux[] = {
2928 MSIOF3_RXD_A_MARK,
2929 };
2930 static const unsigned int msiof3_clk_b_pins[] = {
2931 /* SCK */
2932 RCAR_GP_PIN(1, 2),
2933 };
2934 static const unsigned int msiof3_clk_b_mux[] = {
2935 MSIOF3_SCK_B_MARK,
2936 };
2937 static const unsigned int msiof3_sync_b_pins[] = {
2938 /* SYNC */
2939 RCAR_GP_PIN(1, 0),
2940 };
2941 static const unsigned int msiof3_sync_b_mux[] = {
2942 MSIOF3_SYNC_B_MARK,
2943 };
2944 static const unsigned int msiof3_ss1_b_pins[] = {
2945 /* SS1 */
2946 RCAR_GP_PIN(1, 4),
2947 };
2948 static const unsigned int msiof3_ss1_b_mux[] = {
2949 MSIOF3_SS1_B_MARK,
2950 };
2951 static const unsigned int msiof3_ss2_b_pins[] = {
2952 /* SS2 */
2953 RCAR_GP_PIN(1, 5),
2954 };
2955 static const unsigned int msiof3_ss2_b_mux[] = {
2956 MSIOF3_SS2_B_MARK,
2957 };
2958 static const unsigned int msiof3_txd_b_pins[] = {
2959 /* TXD */
2960 RCAR_GP_PIN(1, 1),
2961 };
2962 static const unsigned int msiof3_txd_b_mux[] = {
2963 MSIOF3_TXD_B_MARK,
2964 };
2965 static const unsigned int msiof3_rxd_b_pins[] = {
2966 /* RXD */
2967 RCAR_GP_PIN(1, 3),
2968 };
2969 static const unsigned int msiof3_rxd_b_mux[] = {
2970 MSIOF3_RXD_B_MARK,
2971 };
2972 static const unsigned int msiof3_clk_c_pins[] = {
2973 /* SCK */
2974 RCAR_GP_PIN(1, 12),
2975 };
2976 static const unsigned int msiof3_clk_c_mux[] = {
2977 MSIOF3_SCK_C_MARK,
2978 };
2979 static const unsigned int msiof3_sync_c_pins[] = {
2980 /* SYNC */
2981 RCAR_GP_PIN(1, 13),
2982 };
2983 static const unsigned int msiof3_sync_c_mux[] = {
2984 MSIOF3_SYNC_C_MARK,
2985 };
2986 static const unsigned int msiof3_txd_c_pins[] = {
2987 /* TXD */
2988 RCAR_GP_PIN(1, 15),
2989 };
2990 static const unsigned int msiof3_txd_c_mux[] = {
2991 MSIOF3_TXD_C_MARK,
2992 };
2993 static const unsigned int msiof3_rxd_c_pins[] = {
2994 /* RXD */
2995 RCAR_GP_PIN(1, 14),
2996 };
2997 static const unsigned int msiof3_rxd_c_mux[] = {
2998 MSIOF3_RXD_C_MARK,
2999 };
3000 static const unsigned int msiof3_clk_d_pins[] = {
3001 /* SCK */
3002 RCAR_GP_PIN(1, 22),
3003 };
3004 static const unsigned int msiof3_clk_d_mux[] = {
3005 MSIOF3_SCK_D_MARK,
3006 };
3007 static const unsigned int msiof3_sync_d_pins[] = {
3008 /* SYNC */
3009 RCAR_GP_PIN(1, 23),
3010 };
3011 static const unsigned int msiof3_sync_d_mux[] = {
3012 MSIOF3_SYNC_D_MARK,
3013 };
3014 static const unsigned int msiof3_ss1_d_pins[] = {
3015 /* SS1 */
3016 RCAR_GP_PIN(1, 26),
3017 };
3018 static const unsigned int msiof3_ss1_d_mux[] = {
3019 MSIOF3_SS1_D_MARK,
3020 };
3021 static const unsigned int msiof3_txd_d_pins[] = {
3022 /* TXD */
3023 RCAR_GP_PIN(1, 25),
3024 };
3025 static const unsigned int msiof3_txd_d_mux[] = {
3026 MSIOF3_TXD_D_MARK,
3027 };
3028 static const unsigned int msiof3_rxd_d_pins[] = {
3029 /* RXD */
3030 RCAR_GP_PIN(1, 24),
3031 };
3032 static const unsigned int msiof3_rxd_d_mux[] = {
3033 MSIOF3_RXD_D_MARK,
3034 };
3035
3036 /* - PWM0 --------------------------------------------------------------------*/
3037 static const unsigned int pwm0_pins[] = {
3038 /* PWM */
3039 RCAR_GP_PIN(2, 6),
3040 };
3041 static const unsigned int pwm0_mux[] = {
3042 PWM0_MARK,
3043 };
3044 /* - PWM1 --------------------------------------------------------------------*/
3045 static const unsigned int pwm1_a_pins[] = {
3046 /* PWM */
3047 RCAR_GP_PIN(2, 7),
3048 };
3049 static const unsigned int pwm1_a_mux[] = {
3050 PWM1_A_MARK,
3051 };
3052 static const unsigned int pwm1_b_pins[] = {
3053 /* PWM */
3054 RCAR_GP_PIN(1, 8),
3055 };
3056 static const unsigned int pwm1_b_mux[] = {
3057 PWM1_B_MARK,
3058 };
3059 /* - PWM2 --------------------------------------------------------------------*/
3060 static const unsigned int pwm2_a_pins[] = {
3061 /* PWM */
3062 RCAR_GP_PIN(2, 8),
3063 };
3064 static const unsigned int pwm2_a_mux[] = {
3065 PWM2_A_MARK,
3066 };
3067 static const unsigned int pwm2_b_pins[] = {
3068 /* PWM */
3069 RCAR_GP_PIN(1, 11),
3070 };
3071 static const unsigned int pwm2_b_mux[] = {
3072 PWM2_B_MARK,
3073 };
3074 /* - PWM3 --------------------------------------------------------------------*/
3075 static const unsigned int pwm3_a_pins[] = {
3076 /* PWM */
3077 RCAR_GP_PIN(1, 0),
3078 };
3079 static const unsigned int pwm3_a_mux[] = {
3080 PWM3_A_MARK,
3081 };
3082 static const unsigned int pwm3_b_pins[] = {
3083 /* PWM */
3084 RCAR_GP_PIN(2, 2),
3085 };
3086 static const unsigned int pwm3_b_mux[] = {
3087 PWM3_B_MARK,
3088 };
3089 /* - PWM4 --------------------------------------------------------------------*/
3090 static const unsigned int pwm4_a_pins[] = {
3091 /* PWM */
3092 RCAR_GP_PIN(1, 1),
3093 };
3094 static const unsigned int pwm4_a_mux[] = {
3095 PWM4_A_MARK,
3096 };
3097 static const unsigned int pwm4_b_pins[] = {
3098 /* PWM */
3099 RCAR_GP_PIN(2, 3),
3100 };
3101 static const unsigned int pwm4_b_mux[] = {
3102 PWM4_B_MARK,
3103 };
3104 /* - PWM5 --------------------------------------------------------------------*/
3105 static const unsigned int pwm5_a_pins[] = {
3106 /* PWM */
3107 RCAR_GP_PIN(1, 2),
3108 };
3109 static const unsigned int pwm5_a_mux[] = {
3110 PWM5_A_MARK,
3111 };
3112 static const unsigned int pwm5_b_pins[] = {
3113 /* PWM */
3114 RCAR_GP_PIN(2, 4),
3115 };
3116 static const unsigned int pwm5_b_mux[] = {
3117 PWM5_B_MARK,
3118 };
3119 /* - PWM6 --------------------------------------------------------------------*/
3120 static const unsigned int pwm6_a_pins[] = {
3121 /* PWM */
3122 RCAR_GP_PIN(1, 3),
3123 };
3124 static const unsigned int pwm6_a_mux[] = {
3125 PWM6_A_MARK,
3126 };
3127 static const unsigned int pwm6_b_pins[] = {
3128 /* PWM */
3129 RCAR_GP_PIN(2, 5),
3130 };
3131 static const unsigned int pwm6_b_mux[] = {
3132 PWM6_B_MARK,
3133 };
3134
3135 /* - QSPI0 ------------------------------------------------------------------ */
3136 static const unsigned int qspi0_ctrl_pins[] = {
3137 /* QSPI0_SPCLK, QSPI0_SSL */
3138 PIN_QSPI0_SPCLK, PIN_QSPI0_SSL,
3139 };
3140 static const unsigned int qspi0_ctrl_mux[] = {
3141 QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
3142 };
3143 static const unsigned int qspi0_data_pins[] = {
3144 /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1, QSPI0_IO2, QSPI0_IO3 */
3145 PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1, PIN_QSPI0_IO2, PIN_QSPI0_IO3,
3146 };
3147 static const unsigned int qspi0_data_mux[] = {
3148 QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
3149 QSPI0_IO2_MARK, QSPI0_IO3_MARK,
3150 };
3151 /* - QSPI1 ------------------------------------------------------------------ */
3152 static const unsigned int qspi1_ctrl_pins[] = {
3153 /* QSPI1_SPCLK, QSPI1_SSL */
3154 PIN_QSPI1_SPCLK, PIN_QSPI1_SSL,
3155 };
3156 static const unsigned int qspi1_ctrl_mux[] = {
3157 QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
3158 };
3159 static const unsigned int qspi1_data_pins[] = {
3160 /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1, QSPI1_IO2, QSPI1_IO3 */
3161 PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1, PIN_QSPI1_IO2, PIN_QSPI1_IO3,
3162 };
3163 static const unsigned int qspi1_data_mux[] = {
3164 QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
3165 QSPI1_IO2_MARK, QSPI1_IO3_MARK,
3166 };
3167
3168 /* - SATA --------------------------------------------------------------------*/
3169 static const unsigned int sata0_devslp_a_pins[] = {
3170 /* DEVSLP */
3171 RCAR_GP_PIN(6, 16),
3172 };
3173 static const unsigned int sata0_devslp_a_mux[] = {
3174 SATA_DEVSLP_A_MARK,
3175 };
3176 static const unsigned int sata0_devslp_b_pins[] = {
3177 /* DEVSLP */
3178 RCAR_GP_PIN(4, 6),
3179 };
3180 static const unsigned int sata0_devslp_b_mux[] = {
3181 SATA_DEVSLP_B_MARK,
3182 };
3183
3184 /* - SCIF0 ------------------------------------------------------------------ */
3185 static const unsigned int scif0_data_pins[] = {
3186 /* RX, TX */
3187 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
3188 };
3189 static const unsigned int scif0_data_mux[] = {
3190 RX0_MARK, TX0_MARK,
3191 };
3192 static const unsigned int scif0_clk_pins[] = {
3193 /* SCK */
3194 RCAR_GP_PIN(5, 0),
3195 };
3196 static const unsigned int scif0_clk_mux[] = {
3197 SCK0_MARK,
3198 };
3199 static const unsigned int scif0_ctrl_pins[] = {
3200 /* RTS, CTS */
3201 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
3202 };
3203 static const unsigned int scif0_ctrl_mux[] = {
3204 RTS0_N_MARK, CTS0_N_MARK,
3205 };
3206 /* - SCIF1 ------------------------------------------------------------------ */
3207 static const unsigned int scif1_data_a_pins[] = {
3208 /* RX, TX */
3209 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
3210 };
3211 static const unsigned int scif1_data_a_mux[] = {
3212 RX1_A_MARK, TX1_A_MARK,
3213 };
3214 static const unsigned int scif1_clk_pins[] = {
3215 /* SCK */
3216 RCAR_GP_PIN(6, 21),
3217 };
3218 static const unsigned int scif1_clk_mux[] = {
3219 SCK1_MARK,
3220 };
3221 static const unsigned int scif1_ctrl_pins[] = {
3222 /* RTS, CTS */
3223 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
3224 };
3225 static const unsigned int scif1_ctrl_mux[] = {
3226 RTS1_N_MARK, CTS1_N_MARK,
3227 };
3228
3229 static const unsigned int scif1_data_b_pins[] = {
3230 /* RX, TX */
3231 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
3232 };
3233 static const unsigned int scif1_data_b_mux[] = {
3234 RX1_B_MARK, TX1_B_MARK,
3235 };
3236 /* - SCIF2 ------------------------------------------------------------------ */
3237 static const unsigned int scif2_data_a_pins[] = {
3238 /* RX, TX */
3239 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
3240 };
3241 static const unsigned int scif2_data_a_mux[] = {
3242 RX2_A_MARK, TX2_A_MARK,
3243 };
3244 static const unsigned int scif2_clk_pins[] = {
3245 /* SCK */
3246 RCAR_GP_PIN(5, 9),
3247 };
3248 static const unsigned int scif2_clk_mux[] = {
3249 SCK2_MARK,
3250 };
3251 static const unsigned int scif2_data_b_pins[] = {
3252 /* RX, TX */
3253 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3254 };
3255 static const unsigned int scif2_data_b_mux[] = {
3256 RX2_B_MARK, TX2_B_MARK,
3257 };
3258 /* - SCIF3 ------------------------------------------------------------------ */
3259 static const unsigned int scif3_data_a_pins[] = {
3260 /* RX, TX */
3261 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
3262 };
3263 static const unsigned int scif3_data_a_mux[] = {
3264 RX3_A_MARK, TX3_A_MARK,
3265 };
3266 static const unsigned int scif3_clk_pins[] = {
3267 /* SCK */
3268 RCAR_GP_PIN(1, 22),
3269 };
3270 static const unsigned int scif3_clk_mux[] = {
3271 SCK3_MARK,
3272 };
3273 static const unsigned int scif3_ctrl_pins[] = {
3274 /* RTS, CTS */
3275 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
3276 };
3277 static const unsigned int scif3_ctrl_mux[] = {
3278 RTS3_N_MARK, CTS3_N_MARK,
3279 };
3280 static const unsigned int scif3_data_b_pins[] = {
3281 /* RX, TX */
3282 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
3283 };
3284 static const unsigned int scif3_data_b_mux[] = {
3285 RX3_B_MARK, TX3_B_MARK,
3286 };
3287 /* - SCIF4 ------------------------------------------------------------------ */
3288 static const unsigned int scif4_data_a_pins[] = {
3289 /* RX, TX */
3290 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
3291 };
3292 static const unsigned int scif4_data_a_mux[] = {
3293 RX4_A_MARK, TX4_A_MARK,
3294 };
3295 static const unsigned int scif4_clk_a_pins[] = {
3296 /* SCK */
3297 RCAR_GP_PIN(2, 10),
3298 };
3299 static const unsigned int scif4_clk_a_mux[] = {
3300 SCK4_A_MARK,
3301 };
3302 static const unsigned int scif4_ctrl_a_pins[] = {
3303 /* RTS, CTS */
3304 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
3305 };
3306 static const unsigned int scif4_ctrl_a_mux[] = {
3307 RTS4_N_A_MARK, CTS4_N_A_MARK,
3308 };
3309 static const unsigned int scif4_data_b_pins[] = {
3310 /* RX, TX */
3311 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3312 };
3313 static const unsigned int scif4_data_b_mux[] = {
3314 RX4_B_MARK, TX4_B_MARK,
3315 };
3316 static const unsigned int scif4_clk_b_pins[] = {
3317 /* SCK */
3318 RCAR_GP_PIN(1, 5),
3319 };
3320 static const unsigned int scif4_clk_b_mux[] = {
3321 SCK4_B_MARK,
3322 };
3323 static const unsigned int scif4_ctrl_b_pins[] = {
3324 /* RTS, CTS */
3325 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
3326 };
3327 static const unsigned int scif4_ctrl_b_mux[] = {
3328 RTS4_N_B_MARK, CTS4_N_B_MARK,
3329 };
3330 static const unsigned int scif4_data_c_pins[] = {
3331 /* RX, TX */
3332 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3333 };
3334 static const unsigned int scif4_data_c_mux[] = {
3335 RX4_C_MARK, TX4_C_MARK,
3336 };
3337 static const unsigned int scif4_clk_c_pins[] = {
3338 /* SCK */
3339 RCAR_GP_PIN(0, 8),
3340 };
3341 static const unsigned int scif4_clk_c_mux[] = {
3342 SCK4_C_MARK,
3343 };
3344 static const unsigned int scif4_ctrl_c_pins[] = {
3345 /* RTS, CTS */
3346 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
3347 };
3348 static const unsigned int scif4_ctrl_c_mux[] = {
3349 RTS4_N_C_MARK, CTS4_N_C_MARK,
3350 };
3351 /* - SCIF5 ------------------------------------------------------------------ */
3352 static const unsigned int scif5_data_pins[] = {
3353 /* RX, TX */
3354 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3355 };
3356 static const unsigned int scif5_data_mux[] = {
3357 RX5_MARK, TX5_MARK,
3358 };
3359 static const unsigned int scif5_clk_pins[] = {
3360 /* SCK */
3361 RCAR_GP_PIN(6, 21),
3362 };
3363 static const unsigned int scif5_clk_mux[] = {
3364 SCK5_MARK,
3365 };
3366
3367 /* - SCIF Clock ------------------------------------------------------------- */
3368 static const unsigned int scif_clk_a_pins[] = {
3369 /* SCIF_CLK */
3370 RCAR_GP_PIN(6, 23),
3371 };
3372 static const unsigned int scif_clk_a_mux[] = {
3373 SCIF_CLK_A_MARK,
3374 };
3375 static const unsigned int scif_clk_b_pins[] = {
3376 /* SCIF_CLK */
3377 RCAR_GP_PIN(5, 9),
3378 };
3379 static const unsigned int scif_clk_b_mux[] = {
3380 SCIF_CLK_B_MARK,
3381 };
3382
3383 /* - SDHI0 ------------------------------------------------------------------ */
3384 static const unsigned int sdhi0_data_pins[] = {
3385 /* D[0:3] */
3386 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3387 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
3388 };
3389 static const unsigned int sdhi0_data_mux[] = {
3390 SD0_DAT0_MARK, SD0_DAT1_MARK,
3391 SD0_DAT2_MARK, SD0_DAT3_MARK,
3392 };
3393 static const unsigned int sdhi0_ctrl_pins[] = {
3394 /* CLK, CMD */
3395 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3396 };
3397 static const unsigned int sdhi0_ctrl_mux[] = {
3398 SD0_CLK_MARK, SD0_CMD_MARK,
3399 };
3400 static const unsigned int sdhi0_cd_pins[] = {
3401 /* CD */
3402 RCAR_GP_PIN(3, 12),
3403 };
3404 static const unsigned int sdhi0_cd_mux[] = {
3405 SD0_CD_MARK,
3406 };
3407 static const unsigned int sdhi0_wp_pins[] = {
3408 /* WP */
3409 RCAR_GP_PIN(3, 13),
3410 };
3411 static const unsigned int sdhi0_wp_mux[] = {
3412 SD0_WP_MARK,
3413 };
3414 /* - SDHI1 ------------------------------------------------------------------ */
3415 static const unsigned int sdhi1_data_pins[] = {
3416 /* D[0:3] */
3417 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3418 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3419 };
3420 static const unsigned int sdhi1_data_mux[] = {
3421 SD1_DAT0_MARK, SD1_DAT1_MARK,
3422 SD1_DAT2_MARK, SD1_DAT3_MARK,
3423 };
3424 static const unsigned int sdhi1_ctrl_pins[] = {
3425 /* CLK, CMD */
3426 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
3427 };
3428 static const unsigned int sdhi1_ctrl_mux[] = {
3429 SD1_CLK_MARK, SD1_CMD_MARK,
3430 };
3431 static const unsigned int sdhi1_cd_pins[] = {
3432 /* CD */
3433 RCAR_GP_PIN(3, 14),
3434 };
3435 static const unsigned int sdhi1_cd_mux[] = {
3436 SD1_CD_MARK,
3437 };
3438 static const unsigned int sdhi1_wp_pins[] = {
3439 /* WP */
3440 RCAR_GP_PIN(3, 15),
3441 };
3442 static const unsigned int sdhi1_wp_mux[] = {
3443 SD1_WP_MARK,
3444 };
3445 /* - SDHI2 ------------------------------------------------------------------ */
3446 static const unsigned int sdhi2_data_pins[] = {
3447 /* D[0:7] */
3448 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3449 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3450 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3451 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3452 };
3453 static const unsigned int sdhi2_data_mux[] = {
3454 SD2_DAT0_MARK, SD2_DAT1_MARK,
3455 SD2_DAT2_MARK, SD2_DAT3_MARK,
3456 SD2_DAT4_MARK, SD2_DAT5_MARK,
3457 SD2_DAT6_MARK, SD2_DAT7_MARK,
3458 };
3459 static const unsigned int sdhi2_ctrl_pins[] = {
3460 /* CLK, CMD */
3461 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
3462 };
3463 static const unsigned int sdhi2_ctrl_mux[] = {
3464 SD2_CLK_MARK, SD2_CMD_MARK,
3465 };
3466 static const unsigned int sdhi2_cd_a_pins[] = {
3467 /* CD */
3468 RCAR_GP_PIN(4, 13),
3469 };
3470 static const unsigned int sdhi2_cd_a_mux[] = {
3471 SD2_CD_A_MARK,
3472 };
3473 static const unsigned int sdhi2_cd_b_pins[] = {
3474 /* CD */
3475 RCAR_GP_PIN(5, 10),
3476 };
3477 static const unsigned int sdhi2_cd_b_mux[] = {
3478 SD2_CD_B_MARK,
3479 };
3480 static const unsigned int sdhi2_wp_a_pins[] = {
3481 /* WP */
3482 RCAR_GP_PIN(4, 14),
3483 };
3484 static const unsigned int sdhi2_wp_a_mux[] = {
3485 SD2_WP_A_MARK,
3486 };
3487 static const unsigned int sdhi2_wp_b_pins[] = {
3488 /* WP */
3489 RCAR_GP_PIN(5, 11),
3490 };
3491 static const unsigned int sdhi2_wp_b_mux[] = {
3492 SD2_WP_B_MARK,
3493 };
3494 static const unsigned int sdhi2_ds_pins[] = {
3495 /* DS */
3496 RCAR_GP_PIN(4, 6),
3497 };
3498 static const unsigned int sdhi2_ds_mux[] = {
3499 SD2_DS_MARK,
3500 };
3501 /* - SDHI3 ------------------------------------------------------------------ */
3502 static const unsigned int sdhi3_data_pins[] = {
3503 /* D[0:7] */
3504 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3505 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3506 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
3507 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
3508 };
3509 static const unsigned int sdhi3_data_mux[] = {
3510 SD3_DAT0_MARK, SD3_DAT1_MARK,
3511 SD3_DAT2_MARK, SD3_DAT3_MARK,
3512 SD3_DAT4_MARK, SD3_DAT5_MARK,
3513 SD3_DAT6_MARK, SD3_DAT7_MARK,
3514 };
3515 static const unsigned int sdhi3_ctrl_pins[] = {
3516 /* CLK, CMD */
3517 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
3518 };
3519 static const unsigned int sdhi3_ctrl_mux[] = {
3520 SD3_CLK_MARK, SD3_CMD_MARK,
3521 };
3522 static const unsigned int sdhi3_cd_pins[] = {
3523 /* CD */
3524 RCAR_GP_PIN(4, 15),
3525 };
3526 static const unsigned int sdhi3_cd_mux[] = {
3527 SD3_CD_MARK,
3528 };
3529 static const unsigned int sdhi3_wp_pins[] = {
3530 /* WP */
3531 RCAR_GP_PIN(4, 16),
3532 };
3533 static const unsigned int sdhi3_wp_mux[] = {
3534 SD3_WP_MARK,
3535 };
3536 static const unsigned int sdhi3_ds_pins[] = {
3537 /* DS */
3538 RCAR_GP_PIN(4, 17),
3539 };
3540 static const unsigned int sdhi3_ds_mux[] = {
3541 SD3_DS_MARK,
3542 };
3543
3544 /* - SSI -------------------------------------------------------------------- */
3545 static const unsigned int ssi0_data_pins[] = {
3546 /* SDATA */
3547 RCAR_GP_PIN(6, 2),
3548 };
3549 static const unsigned int ssi0_data_mux[] = {
3550 SSI_SDATA0_MARK,
3551 };
3552 static const unsigned int ssi01239_ctrl_pins[] = {
3553 /* SCK, WS */
3554 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3555 };
3556 static const unsigned int ssi01239_ctrl_mux[] = {
3557 SSI_SCK01239_MARK, SSI_WS01239_MARK,
3558 };
3559 static const unsigned int ssi1_data_a_pins[] = {
3560 /* SDATA */
3561 RCAR_GP_PIN(6, 3),
3562 };
3563 static const unsigned int ssi1_data_a_mux[] = {
3564 SSI_SDATA1_A_MARK,
3565 };
3566 static const unsigned int ssi1_data_b_pins[] = {
3567 /* SDATA */
3568 RCAR_GP_PIN(5, 12),
3569 };
3570 static const unsigned int ssi1_data_b_mux[] = {
3571 SSI_SDATA1_B_MARK,
3572 };
3573 static const unsigned int ssi1_ctrl_a_pins[] = {
3574 /* SCK, WS */
3575 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3576 };
3577 static const unsigned int ssi1_ctrl_a_mux[] = {
3578 SSI_SCK1_A_MARK, SSI_WS1_A_MARK,
3579 };
3580 static const unsigned int ssi1_ctrl_b_pins[] = {
3581 /* SCK, WS */
3582 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21),
3583 };
3584 static const unsigned int ssi1_ctrl_b_mux[] = {
3585 SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
3586 };
3587 static const unsigned int ssi2_data_a_pins[] = {
3588 /* SDATA */
3589 RCAR_GP_PIN(6, 4),
3590 };
3591 static const unsigned int ssi2_data_a_mux[] = {
3592 SSI_SDATA2_A_MARK,
3593 };
3594 static const unsigned int ssi2_data_b_pins[] = {
3595 /* SDATA */
3596 RCAR_GP_PIN(5, 13),
3597 };
3598 static const unsigned int ssi2_data_b_mux[] = {
3599 SSI_SDATA2_B_MARK,
3600 };
3601 static const unsigned int ssi2_ctrl_a_pins[] = {
3602 /* SCK, WS */
3603 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3604 };
3605 static const unsigned int ssi2_ctrl_a_mux[] = {
3606 SSI_SCK2_A_MARK, SSI_WS2_A_MARK,
3607 };
3608 static const unsigned int ssi2_ctrl_b_pins[] = {
3609 /* SCK, WS */
3610 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3611 };
3612 static const unsigned int ssi2_ctrl_b_mux[] = {
3613 SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
3614 };
3615 static const unsigned int ssi3_data_pins[] = {
3616 /* SDATA */
3617 RCAR_GP_PIN(6, 7),
3618 };
3619 static const unsigned int ssi3_data_mux[] = {
3620 SSI_SDATA3_MARK,
3621 };
3622 static const unsigned int ssi349_ctrl_pins[] = {
3623 /* SCK, WS */
3624 RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
3625 };
3626 static const unsigned int ssi349_ctrl_mux[] = {
3627 SSI_SCK349_MARK, SSI_WS349_MARK,
3628 };
3629 static const unsigned int ssi4_data_pins[] = {
3630 /* SDATA */
3631 RCAR_GP_PIN(6, 10),
3632 };
3633 static const unsigned int ssi4_data_mux[] = {
3634 SSI_SDATA4_MARK,
3635 };
3636 static const unsigned int ssi4_ctrl_pins[] = {
3637 /* SCK, WS */
3638 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
3639 };
3640 static const unsigned int ssi4_ctrl_mux[] = {
3641 SSI_SCK4_MARK, SSI_WS4_MARK,
3642 };
3643 static const unsigned int ssi5_data_pins[] = {
3644 /* SDATA */
3645 RCAR_GP_PIN(6, 13),
3646 };
3647 static const unsigned int ssi5_data_mux[] = {
3648 SSI_SDATA5_MARK,
3649 };
3650 static const unsigned int ssi5_ctrl_pins[] = {
3651 /* SCK, WS */
3652 RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
3653 };
3654 static const unsigned int ssi5_ctrl_mux[] = {
3655 SSI_SCK5_MARK, SSI_WS5_MARK,
3656 };
3657 static const unsigned int ssi6_data_pins[] = {
3658 /* SDATA */
3659 RCAR_GP_PIN(6, 16),
3660 };
3661 static const unsigned int ssi6_data_mux[] = {
3662 SSI_SDATA6_MARK,
3663 };
3664 static const unsigned int ssi6_ctrl_pins[] = {
3665 /* SCK, WS */
3666 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3667 };
3668 static const unsigned int ssi6_ctrl_mux[] = {
3669 SSI_SCK6_MARK, SSI_WS6_MARK,
3670 };
3671 static const unsigned int ssi7_data_pins[] = {
3672 /* SDATA */
3673 RCAR_GP_PIN(6, 19),
3674 };
3675 static const unsigned int ssi7_data_mux[] = {
3676 SSI_SDATA7_MARK,
3677 };
3678 static const unsigned int ssi78_ctrl_pins[] = {
3679 /* SCK, WS */
3680 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
3681 };
3682 static const unsigned int ssi78_ctrl_mux[] = {
3683 SSI_SCK78_MARK, SSI_WS78_MARK,
3684 };
3685 static const unsigned int ssi8_data_pins[] = {
3686 /* SDATA */
3687 RCAR_GP_PIN(6, 20),
3688 };
3689 static const unsigned int ssi8_data_mux[] = {
3690 SSI_SDATA8_MARK,
3691 };
3692 static const unsigned int ssi9_data_a_pins[] = {
3693 /* SDATA */
3694 RCAR_GP_PIN(6, 21),
3695 };
3696 static const unsigned int ssi9_data_a_mux[] = {
3697 SSI_SDATA9_A_MARK,
3698 };
3699 static const unsigned int ssi9_data_b_pins[] = {
3700 /* SDATA */
3701 RCAR_GP_PIN(5, 14),
3702 };
3703 static const unsigned int ssi9_data_b_mux[] = {
3704 SSI_SDATA9_B_MARK,
3705 };
3706 static const unsigned int ssi9_ctrl_a_pins[] = {
3707 /* SCK, WS */
3708 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3709 };
3710 static const unsigned int ssi9_ctrl_a_mux[] = {
3711 SSI_SCK9_A_MARK, SSI_WS9_A_MARK,
3712 };
3713 static const unsigned int ssi9_ctrl_b_pins[] = {
3714 /* SCK, WS */
3715 RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
3716 };
3717 static const unsigned int ssi9_ctrl_b_mux[] = {
3718 SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
3719 };
3720
3721 /* - TMU -------------------------------------------------------------------- */
3722 static const unsigned int tmu_tclk1_a_pins[] = {
3723 /* TCLK */
3724 RCAR_GP_PIN(6, 23),
3725 };
3726 static const unsigned int tmu_tclk1_a_mux[] = {
3727 TCLK1_A_MARK,
3728 };
3729 static const unsigned int tmu_tclk1_b_pins[] = {
3730 /* TCLK */
3731 RCAR_GP_PIN(5, 19),
3732 };
3733 static const unsigned int tmu_tclk1_b_mux[] = {
3734 TCLK1_B_MARK,
3735 };
3736 static const unsigned int tmu_tclk2_a_pins[] = {
3737 /* TCLK */
3738 RCAR_GP_PIN(6, 19),
3739 };
3740 static const unsigned int tmu_tclk2_a_mux[] = {
3741 TCLK2_A_MARK,
3742 };
3743 static const unsigned int tmu_tclk2_b_pins[] = {
3744 /* TCLK */
3745 RCAR_GP_PIN(6, 28),
3746 };
3747 static const unsigned int tmu_tclk2_b_mux[] = {
3748 TCLK2_B_MARK,
3749 };
3750
3751 /* - TPU ------------------------------------------------------------------- */
3752 static const unsigned int tpu_to0_pins[] = {
3753 /* TPU0TO0 */
3754 RCAR_GP_PIN(6, 28),
3755 };
3756 static const unsigned int tpu_to0_mux[] = {
3757 TPU0TO0_MARK,
3758 };
3759 static const unsigned int tpu_to1_pins[] = {
3760 /* TPU0TO1 */
3761 RCAR_GP_PIN(6, 29),
3762 };
3763 static const unsigned int tpu_to1_mux[] = {
3764 TPU0TO1_MARK,
3765 };
3766 static const unsigned int tpu_to2_pins[] = {
3767 /* TPU0TO2 */
3768 RCAR_GP_PIN(6, 30),
3769 };
3770 static const unsigned int tpu_to2_mux[] = {
3771 TPU0TO2_MARK,
3772 };
3773 static const unsigned int tpu_to3_pins[] = {
3774 /* TPU0TO3 */
3775 RCAR_GP_PIN(6, 31),
3776 };
3777 static const unsigned int tpu_to3_mux[] = {
3778 TPU0TO3_MARK,
3779 };
3780
3781 /* - USB0 ------------------------------------------------------------------- */
3782 static const unsigned int usb0_pins[] = {
3783 /* PWEN, OVC */
3784 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
3785 };
3786 static const unsigned int usb0_mux[] = {
3787 USB0_PWEN_MARK, USB0_OVC_MARK,
3788 };
3789 /* - USB1 ------------------------------------------------------------------- */
3790 static const unsigned int usb1_pins[] = {
3791 /* PWEN, OVC */
3792 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3793 };
3794 static const unsigned int usb1_mux[] = {
3795 USB1_PWEN_MARK, USB1_OVC_MARK,
3796 };
3797 /* - USB2 ------------------------------------------------------------------- */
3798 static const unsigned int usb2_pins[] = {
3799 /* PWEN, OVC */
3800 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3801 };
3802 static const unsigned int usb2_mux[] = {
3803 USB2_PWEN_MARK, USB2_OVC_MARK,
3804 };
3805
3806 /* - USB30 ------------------------------------------------------------------ */
3807 static const unsigned int usb30_pins[] = {
3808 /* PWEN, OVC */
3809 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3810 };
3811 static const unsigned int usb30_mux[] = {
3812 USB30_PWEN_MARK, USB30_OVC_MARK,
3813 };
3814 /* - USB31 ------------------------------------------------------------------ */
3815 static const unsigned int usb31_pins[] = {
3816 /* PWEN, OVC */
3817 RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
3818 };
3819 static const unsigned int usb31_mux[] = {
3820 USB31_PWEN_MARK, USB31_OVC_MARK,
3821 };
3822
3823 static const struct sh_pfc_pin_group pinmux_groups[] = {
3824 SH_PFC_PIN_GROUP(audio_clk_a_a),
3825 SH_PFC_PIN_GROUP(audio_clk_a_b),
3826 SH_PFC_PIN_GROUP(audio_clk_a_c),
3827 SH_PFC_PIN_GROUP(audio_clk_b_a),
3828 SH_PFC_PIN_GROUP(audio_clk_b_b),
3829 SH_PFC_PIN_GROUP(audio_clk_c_a),
3830 SH_PFC_PIN_GROUP(audio_clk_c_b),
3831 SH_PFC_PIN_GROUP(audio_clkout_a),
3832 SH_PFC_PIN_GROUP(audio_clkout_b),
3833 SH_PFC_PIN_GROUP(audio_clkout_c),
3834 SH_PFC_PIN_GROUP(audio_clkout_d),
3835 SH_PFC_PIN_GROUP(audio_clkout1_a),
3836 SH_PFC_PIN_GROUP(audio_clkout1_b),
3837 SH_PFC_PIN_GROUP(audio_clkout2_a),
3838 SH_PFC_PIN_GROUP(audio_clkout2_b),
3839 SH_PFC_PIN_GROUP(audio_clkout3_a),
3840 SH_PFC_PIN_GROUP(audio_clkout3_b),
3841 SH_PFC_PIN_GROUP(avb_link),
3842 SH_PFC_PIN_GROUP(avb_magic),
3843 SH_PFC_PIN_GROUP(avb_phy_int),
3844 SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio), /* Deprecated */
3845 SH_PFC_PIN_GROUP(avb_mdio),
3846 SH_PFC_PIN_GROUP(avb_mii),
3847 SH_PFC_PIN_GROUP(avb_avtp_pps),
3848 SH_PFC_PIN_GROUP(avb_avtp_match_a),
3849 SH_PFC_PIN_GROUP(avb_avtp_capture_a),
3850 SH_PFC_PIN_GROUP(avb_avtp_match_b),
3851 SH_PFC_PIN_GROUP(avb_avtp_capture_b),
3852 SH_PFC_PIN_GROUP(can0_data_a),
3853 SH_PFC_PIN_GROUP(can0_data_b),
3854 SH_PFC_PIN_GROUP(can1_data),
3855 SH_PFC_PIN_GROUP(can_clk),
3856 SH_PFC_PIN_GROUP(canfd0_data_a),
3857 SH_PFC_PIN_GROUP(canfd0_data_b),
3858 SH_PFC_PIN_GROUP(canfd1_data),
3859 SH_PFC_PIN_GROUP(drif0_ctrl_a),
3860 SH_PFC_PIN_GROUP(drif0_data0_a),
3861 SH_PFC_PIN_GROUP(drif0_data1_a),
3862 SH_PFC_PIN_GROUP(drif0_ctrl_b),
3863 SH_PFC_PIN_GROUP(drif0_data0_b),
3864 SH_PFC_PIN_GROUP(drif0_data1_b),
3865 SH_PFC_PIN_GROUP(drif0_ctrl_c),
3866 SH_PFC_PIN_GROUP(drif0_data0_c),
3867 SH_PFC_PIN_GROUP(drif0_data1_c),
3868 SH_PFC_PIN_GROUP(drif1_ctrl_a),
3869 SH_PFC_PIN_GROUP(drif1_data0_a),
3870 SH_PFC_PIN_GROUP(drif1_data1_a),
3871 SH_PFC_PIN_GROUP(drif1_ctrl_b),
3872 SH_PFC_PIN_GROUP(drif1_data0_b),
3873 SH_PFC_PIN_GROUP(drif1_data1_b),
3874 SH_PFC_PIN_GROUP(drif1_ctrl_c),
3875 SH_PFC_PIN_GROUP(drif1_data0_c),
3876 SH_PFC_PIN_GROUP(drif1_data1_c),
3877 SH_PFC_PIN_GROUP(drif2_ctrl_a),
3878 SH_PFC_PIN_GROUP(drif2_data0_a),
3879 SH_PFC_PIN_GROUP(drif2_data1_a),
3880 SH_PFC_PIN_GROUP(drif2_ctrl_b),
3881 SH_PFC_PIN_GROUP(drif2_data0_b),
3882 SH_PFC_PIN_GROUP(drif2_data1_b),
3883 SH_PFC_PIN_GROUP(drif3_ctrl_a),
3884 SH_PFC_PIN_GROUP(drif3_data0_a),
3885 SH_PFC_PIN_GROUP(drif3_data1_a),
3886 SH_PFC_PIN_GROUP(drif3_ctrl_b),
3887 SH_PFC_PIN_GROUP(drif3_data0_b),
3888 SH_PFC_PIN_GROUP(drif3_data1_b),
3889 SH_PFC_PIN_GROUP(du_rgb666),
3890 SH_PFC_PIN_GROUP(du_rgb888),
3891 SH_PFC_PIN_GROUP(du_clk_out_0),
3892 SH_PFC_PIN_GROUP(du_clk_out_1),
3893 SH_PFC_PIN_GROUP(du_sync),
3894 SH_PFC_PIN_GROUP(du_oddf),
3895 SH_PFC_PIN_GROUP(du_cde),
3896 SH_PFC_PIN_GROUP(du_disp),
3897 SH_PFC_PIN_GROUP(hscif0_data),
3898 SH_PFC_PIN_GROUP(hscif0_clk),
3899 SH_PFC_PIN_GROUP(hscif0_ctrl),
3900 SH_PFC_PIN_GROUP(hscif1_data_a),
3901 SH_PFC_PIN_GROUP(hscif1_clk_a),
3902 SH_PFC_PIN_GROUP(hscif1_ctrl_a),
3903 SH_PFC_PIN_GROUP(hscif1_data_b),
3904 SH_PFC_PIN_GROUP(hscif1_clk_b),
3905 SH_PFC_PIN_GROUP(hscif1_ctrl_b),
3906 SH_PFC_PIN_GROUP(hscif2_data_a),
3907 SH_PFC_PIN_GROUP(hscif2_clk_a),
3908 SH_PFC_PIN_GROUP(hscif2_ctrl_a),
3909 SH_PFC_PIN_GROUP(hscif2_data_b),
3910 SH_PFC_PIN_GROUP(hscif2_clk_b),
3911 SH_PFC_PIN_GROUP(hscif2_ctrl_b),
3912 SH_PFC_PIN_GROUP(hscif3_data_a),
3913 SH_PFC_PIN_GROUP(hscif3_clk),
3914 SH_PFC_PIN_GROUP(hscif3_ctrl),
3915 SH_PFC_PIN_GROUP(hscif3_data_b),
3916 SH_PFC_PIN_GROUP(hscif3_data_c),
3917 SH_PFC_PIN_GROUP(hscif3_data_d),
3918 SH_PFC_PIN_GROUP(hscif4_data_a),
3919 SH_PFC_PIN_GROUP(hscif4_clk),
3920 SH_PFC_PIN_GROUP(hscif4_ctrl),
3921 SH_PFC_PIN_GROUP(hscif4_data_b),
3922 SH_PFC_PIN_GROUP(i2c0),
3923 SH_PFC_PIN_GROUP(i2c1_a),
3924 SH_PFC_PIN_GROUP(i2c1_b),
3925 SH_PFC_PIN_GROUP(i2c2_a),
3926 SH_PFC_PIN_GROUP(i2c2_b),
3927 SH_PFC_PIN_GROUP(i2c3),
3928 SH_PFC_PIN_GROUP(i2c5),
3929 SH_PFC_PIN_GROUP(i2c6_a),
3930 SH_PFC_PIN_GROUP(i2c6_b),
3931 SH_PFC_PIN_GROUP(i2c6_c),
3932 SH_PFC_PIN_GROUP(intc_ex_irq0),
3933 SH_PFC_PIN_GROUP(intc_ex_irq1),
3934 SH_PFC_PIN_GROUP(intc_ex_irq2),
3935 SH_PFC_PIN_GROUP(intc_ex_irq3),
3936 SH_PFC_PIN_GROUP(intc_ex_irq4),
3937 SH_PFC_PIN_GROUP(intc_ex_irq5),
3938 SH_PFC_PIN_GROUP(mlb_3pin),
3939 SH_PFC_PIN_GROUP(msiof0_clk),
3940 SH_PFC_PIN_GROUP(msiof0_sync),
3941 SH_PFC_PIN_GROUP(msiof0_ss1),
3942 SH_PFC_PIN_GROUP(msiof0_ss2),
3943 SH_PFC_PIN_GROUP(msiof0_txd),
3944 SH_PFC_PIN_GROUP(msiof0_rxd),
3945 SH_PFC_PIN_GROUP(msiof1_clk_a),
3946 SH_PFC_PIN_GROUP(msiof1_sync_a),
3947 SH_PFC_PIN_GROUP(msiof1_ss1_a),
3948 SH_PFC_PIN_GROUP(msiof1_ss2_a),
3949 SH_PFC_PIN_GROUP(msiof1_txd_a),
3950 SH_PFC_PIN_GROUP(msiof1_rxd_a),
3951 SH_PFC_PIN_GROUP(msiof1_clk_b),
3952 SH_PFC_PIN_GROUP(msiof1_sync_b),
3953 SH_PFC_PIN_GROUP(msiof1_ss1_b),
3954 SH_PFC_PIN_GROUP(msiof1_ss2_b),
3955 SH_PFC_PIN_GROUP(msiof1_txd_b),
3956 SH_PFC_PIN_GROUP(msiof1_rxd_b),
3957 SH_PFC_PIN_GROUP(msiof1_clk_c),
3958 SH_PFC_PIN_GROUP(msiof1_sync_c),
3959 SH_PFC_PIN_GROUP(msiof1_ss1_c),
3960 SH_PFC_PIN_GROUP(msiof1_ss2_c),
3961 SH_PFC_PIN_GROUP(msiof1_txd_c),
3962 SH_PFC_PIN_GROUP(msiof1_rxd_c),
3963 SH_PFC_PIN_GROUP(msiof1_clk_d),
3964 SH_PFC_PIN_GROUP(msiof1_sync_d),
3965 SH_PFC_PIN_GROUP(msiof1_ss1_d),
3966 SH_PFC_PIN_GROUP(msiof1_ss2_d),
3967 SH_PFC_PIN_GROUP(msiof1_txd_d),
3968 SH_PFC_PIN_GROUP(msiof1_rxd_d),
3969 SH_PFC_PIN_GROUP(msiof1_clk_e),
3970 SH_PFC_PIN_GROUP(msiof1_sync_e),
3971 SH_PFC_PIN_GROUP(msiof1_ss1_e),
3972 SH_PFC_PIN_GROUP(msiof1_ss2_e),
3973 SH_PFC_PIN_GROUP(msiof1_txd_e),
3974 SH_PFC_PIN_GROUP(msiof1_rxd_e),
3975 SH_PFC_PIN_GROUP(msiof1_clk_f),
3976 SH_PFC_PIN_GROUP(msiof1_sync_f),
3977 SH_PFC_PIN_GROUP(msiof1_ss1_f),
3978 SH_PFC_PIN_GROUP(msiof1_ss2_f),
3979 SH_PFC_PIN_GROUP(msiof1_txd_f),
3980 SH_PFC_PIN_GROUP(msiof1_rxd_f),
3981 SH_PFC_PIN_GROUP(msiof1_clk_g),
3982 SH_PFC_PIN_GROUP(msiof1_sync_g),
3983 SH_PFC_PIN_GROUP(msiof1_ss1_g),
3984 SH_PFC_PIN_GROUP(msiof1_ss2_g),
3985 SH_PFC_PIN_GROUP(msiof1_txd_g),
3986 SH_PFC_PIN_GROUP(msiof1_rxd_g),
3987 SH_PFC_PIN_GROUP(msiof2_clk_a),
3988 SH_PFC_PIN_GROUP(msiof2_sync_a),
3989 SH_PFC_PIN_GROUP(msiof2_ss1_a),
3990 SH_PFC_PIN_GROUP(msiof2_ss2_a),
3991 SH_PFC_PIN_GROUP(msiof2_txd_a),
3992 SH_PFC_PIN_GROUP(msiof2_rxd_a),
3993 SH_PFC_PIN_GROUP(msiof2_clk_b),
3994 SH_PFC_PIN_GROUP(msiof2_sync_b),
3995 SH_PFC_PIN_GROUP(msiof2_ss1_b),
3996 SH_PFC_PIN_GROUP(msiof2_ss2_b),
3997 SH_PFC_PIN_GROUP(msiof2_txd_b),
3998 SH_PFC_PIN_GROUP(msiof2_rxd_b),
3999 SH_PFC_PIN_GROUP(msiof2_clk_c),
4000 SH_PFC_PIN_GROUP(msiof2_sync_c),
4001 SH_PFC_PIN_GROUP(msiof2_ss1_c),
4002 SH_PFC_PIN_GROUP(msiof2_ss2_c),
4003 SH_PFC_PIN_GROUP(msiof2_txd_c),
4004 SH_PFC_PIN_GROUP(msiof2_rxd_c),
4005 SH_PFC_PIN_GROUP(msiof2_clk_d),
4006 SH_PFC_PIN_GROUP(msiof2_sync_d),
4007 SH_PFC_PIN_GROUP(msiof2_ss1_d),
4008 SH_PFC_PIN_GROUP(msiof2_ss2_d),
4009 SH_PFC_PIN_GROUP(msiof2_txd_d),
4010 SH_PFC_PIN_GROUP(msiof2_rxd_d),
4011 SH_PFC_PIN_GROUP(msiof3_clk_a),
4012 SH_PFC_PIN_GROUP(msiof3_sync_a),
4013 SH_PFC_PIN_GROUP(msiof3_ss1_a),
4014 SH_PFC_PIN_GROUP(msiof3_ss2_a),
4015 SH_PFC_PIN_GROUP(msiof3_txd_a),
4016 SH_PFC_PIN_GROUP(msiof3_rxd_a),
4017 SH_PFC_PIN_GROUP(msiof3_clk_b),
4018 SH_PFC_PIN_GROUP(msiof3_sync_b),
4019 SH_PFC_PIN_GROUP(msiof3_ss1_b),
4020 SH_PFC_PIN_GROUP(msiof3_ss2_b),
4021 SH_PFC_PIN_GROUP(msiof3_txd_b),
4022 SH_PFC_PIN_GROUP(msiof3_rxd_b),
4023 SH_PFC_PIN_GROUP(msiof3_clk_c),
4024 SH_PFC_PIN_GROUP(msiof3_sync_c),
4025 SH_PFC_PIN_GROUP(msiof3_txd_c),
4026 SH_PFC_PIN_GROUP(msiof3_rxd_c),
4027 SH_PFC_PIN_GROUP(msiof3_clk_d),
4028 SH_PFC_PIN_GROUP(msiof3_sync_d),
4029 SH_PFC_PIN_GROUP(msiof3_ss1_d),
4030 SH_PFC_PIN_GROUP(msiof3_txd_d),
4031 SH_PFC_PIN_GROUP(msiof3_rxd_d),
4032 SH_PFC_PIN_GROUP(pwm0),
4033 SH_PFC_PIN_GROUP(pwm1_a),
4034 SH_PFC_PIN_GROUP(pwm1_b),
4035 SH_PFC_PIN_GROUP(pwm2_a),
4036 SH_PFC_PIN_GROUP(pwm2_b),
4037 SH_PFC_PIN_GROUP(pwm3_a),
4038 SH_PFC_PIN_GROUP(pwm3_b),
4039 SH_PFC_PIN_GROUP(pwm4_a),
4040 SH_PFC_PIN_GROUP(pwm4_b),
4041 SH_PFC_PIN_GROUP(pwm5_a),
4042 SH_PFC_PIN_GROUP(pwm5_b),
4043 SH_PFC_PIN_GROUP(pwm6_a),
4044 SH_PFC_PIN_GROUP(pwm6_b),
4045 SH_PFC_PIN_GROUP(qspi0_ctrl),
4046 BUS_DATA_PIN_GROUP(qspi0_data, 2),
4047 BUS_DATA_PIN_GROUP(qspi0_data, 4),
4048 SH_PFC_PIN_GROUP(qspi1_ctrl),
4049 BUS_DATA_PIN_GROUP(qspi1_data, 2),
4050 BUS_DATA_PIN_GROUP(qspi1_data, 4),
4051 SH_PFC_PIN_GROUP(sata0_devslp_a),
4052 SH_PFC_PIN_GROUP(sata0_devslp_b),
4053 SH_PFC_PIN_GROUP(scif0_data),
4054 SH_PFC_PIN_GROUP(scif0_clk),
4055 SH_PFC_PIN_GROUP(scif0_ctrl),
4056 SH_PFC_PIN_GROUP(scif1_data_a),
4057 SH_PFC_PIN_GROUP(scif1_clk),
4058 SH_PFC_PIN_GROUP(scif1_ctrl),
4059 SH_PFC_PIN_GROUP(scif1_data_b),
4060 SH_PFC_PIN_GROUP(scif2_data_a),
4061 SH_PFC_PIN_GROUP(scif2_clk),
4062 SH_PFC_PIN_GROUP(scif2_data_b),
4063 SH_PFC_PIN_GROUP(scif3_data_a),
4064 SH_PFC_PIN_GROUP(scif3_clk),
4065 SH_PFC_PIN_GROUP(scif3_ctrl),
4066 SH_PFC_PIN_GROUP(scif3_data_b),
4067 SH_PFC_PIN_GROUP(scif4_data_a),
4068 SH_PFC_PIN_GROUP(scif4_clk_a),
4069 SH_PFC_PIN_GROUP(scif4_ctrl_a),
4070 SH_PFC_PIN_GROUP(scif4_data_b),
4071 SH_PFC_PIN_GROUP(scif4_clk_b),
4072 SH_PFC_PIN_GROUP(scif4_ctrl_b),
4073 SH_PFC_PIN_GROUP(scif4_data_c),
4074 SH_PFC_PIN_GROUP(scif4_clk_c),
4075 SH_PFC_PIN_GROUP(scif4_ctrl_c),
4076 SH_PFC_PIN_GROUP(scif5_data),
4077 SH_PFC_PIN_GROUP(scif5_clk),
4078 SH_PFC_PIN_GROUP(scif_clk_a),
4079 SH_PFC_PIN_GROUP(scif_clk_b),
4080 BUS_DATA_PIN_GROUP(sdhi0_data, 1),
4081 BUS_DATA_PIN_GROUP(sdhi0_data, 4),
4082 SH_PFC_PIN_GROUP(sdhi0_ctrl),
4083 SH_PFC_PIN_GROUP(sdhi0_cd),
4084 SH_PFC_PIN_GROUP(sdhi0_wp),
4085 BUS_DATA_PIN_GROUP(sdhi1_data, 1),
4086 BUS_DATA_PIN_GROUP(sdhi1_data, 4),
4087 SH_PFC_PIN_GROUP(sdhi1_ctrl),
4088 SH_PFC_PIN_GROUP(sdhi1_cd),
4089 SH_PFC_PIN_GROUP(sdhi1_wp),
4090 BUS_DATA_PIN_GROUP(sdhi2_data, 1),
4091 BUS_DATA_PIN_GROUP(sdhi2_data, 4),
4092 BUS_DATA_PIN_GROUP(sdhi2_data, 8),
4093 SH_PFC_PIN_GROUP(sdhi2_ctrl),
4094 SH_PFC_PIN_GROUP(sdhi2_cd_a),
4095 SH_PFC_PIN_GROUP(sdhi2_wp_a),
4096 SH_PFC_PIN_GROUP(sdhi2_cd_b),
4097 SH_PFC_PIN_GROUP(sdhi2_wp_b),
4098 SH_PFC_PIN_GROUP(sdhi2_ds),
4099 BUS_DATA_PIN_GROUP(sdhi3_data, 1),
4100 BUS_DATA_PIN_GROUP(sdhi3_data, 4),
4101 BUS_DATA_PIN_GROUP(sdhi3_data, 8),
4102 SH_PFC_PIN_GROUP(sdhi3_ctrl),
4103 SH_PFC_PIN_GROUP(sdhi3_cd),
4104 SH_PFC_PIN_GROUP(sdhi3_wp),
4105 SH_PFC_PIN_GROUP(sdhi3_ds),
4106 SH_PFC_PIN_GROUP(ssi0_data),
4107 SH_PFC_PIN_GROUP(ssi01239_ctrl),
4108 SH_PFC_PIN_GROUP(ssi1_data_a),
4109 SH_PFC_PIN_GROUP(ssi1_data_b),
4110 SH_PFC_PIN_GROUP(ssi1_ctrl_a),
4111 SH_PFC_PIN_GROUP(ssi1_ctrl_b),
4112 SH_PFC_PIN_GROUP(ssi2_data_a),
4113 SH_PFC_PIN_GROUP(ssi2_data_b),
4114 SH_PFC_PIN_GROUP(ssi2_ctrl_a),
4115 SH_PFC_PIN_GROUP(ssi2_ctrl_b),
4116 SH_PFC_PIN_GROUP(ssi3_data),
4117 SH_PFC_PIN_GROUP(ssi349_ctrl),
4118 SH_PFC_PIN_GROUP(ssi4_data),
4119 SH_PFC_PIN_GROUP(ssi4_ctrl),
4120 SH_PFC_PIN_GROUP(ssi5_data),
4121 SH_PFC_PIN_GROUP(ssi5_ctrl),
4122 SH_PFC_PIN_GROUP(ssi6_data),
4123 SH_PFC_PIN_GROUP(ssi6_ctrl),
4124 SH_PFC_PIN_GROUP(ssi7_data),
4125 SH_PFC_PIN_GROUP(ssi78_ctrl),
4126 SH_PFC_PIN_GROUP(ssi8_data),
4127 SH_PFC_PIN_GROUP(ssi9_data_a),
4128 SH_PFC_PIN_GROUP(ssi9_data_b),
4129 SH_PFC_PIN_GROUP(ssi9_ctrl_a),
4130 SH_PFC_PIN_GROUP(ssi9_ctrl_b),
4131 SH_PFC_PIN_GROUP(tmu_tclk1_a),
4132 SH_PFC_PIN_GROUP(tmu_tclk1_b),
4133 SH_PFC_PIN_GROUP(tmu_tclk2_a),
4134 SH_PFC_PIN_GROUP(tmu_tclk2_b),
4135 SH_PFC_PIN_GROUP(tpu_to0),
4136 SH_PFC_PIN_GROUP(tpu_to1),
4137 SH_PFC_PIN_GROUP(tpu_to2),
4138 SH_PFC_PIN_GROUP(tpu_to3),
4139 SH_PFC_PIN_GROUP(usb0),
4140 SH_PFC_PIN_GROUP(usb1),
4141 SH_PFC_PIN_GROUP(usb2),
4142 SH_PFC_PIN_GROUP(usb30),
4143 SH_PFC_PIN_GROUP(usb31),
4144 };
4145
4146 static const char * const audio_clk_groups[] = {
4147 "audio_clk_a_a",
4148 "audio_clk_a_b",
4149 "audio_clk_a_c",
4150 "audio_clk_b_a",
4151 "audio_clk_b_b",
4152 "audio_clk_c_a",
4153 "audio_clk_c_b",
4154 "audio_clkout_a",
4155 "audio_clkout_b",
4156 "audio_clkout_c",
4157 "audio_clkout_d",
4158 "audio_clkout1_a",
4159 "audio_clkout1_b",
4160 "audio_clkout2_a",
4161 "audio_clkout2_b",
4162 "audio_clkout3_a",
4163 "audio_clkout3_b",
4164 };
4165
4166 static const char * const avb_groups[] = {
4167 "avb_link",
4168 "avb_magic",
4169 "avb_phy_int",
4170 "avb_mdc", /* Deprecated, please use "avb_mdio" instead */
4171 "avb_mdio",
4172 "avb_mii",
4173 "avb_avtp_pps",
4174 "avb_avtp_match_a",
4175 "avb_avtp_capture_a",
4176 "avb_avtp_match_b",
4177 "avb_avtp_capture_b",
4178 };
4179
4180 static const char * const can0_groups[] = {
4181 "can0_data_a",
4182 "can0_data_b",
4183 };
4184
4185 static const char * const can1_groups[] = {
4186 "can1_data",
4187 };
4188
4189 static const char * const can_clk_groups[] = {
4190 "can_clk",
4191 };
4192
4193 static const char * const canfd0_groups[] = {
4194 "canfd0_data_a",
4195 "canfd0_data_b",
4196 };
4197
4198 static const char * const canfd1_groups[] = {
4199 "canfd1_data",
4200 };
4201
4202 static const char * const drif0_groups[] = {
4203 "drif0_ctrl_a",
4204 "drif0_data0_a",
4205 "drif0_data1_a",
4206 "drif0_ctrl_b",
4207 "drif0_data0_b",
4208 "drif0_data1_b",
4209 "drif0_ctrl_c",
4210 "drif0_data0_c",
4211 "drif0_data1_c",
4212 };
4213
4214 static const char * const drif1_groups[] = {
4215 "drif1_ctrl_a",
4216 "drif1_data0_a",
4217 "drif1_data1_a",
4218 "drif1_ctrl_b",
4219 "drif1_data0_b",
4220 "drif1_data1_b",
4221 "drif1_ctrl_c",
4222 "drif1_data0_c",
4223 "drif1_data1_c",
4224 };
4225
4226 static const char * const drif2_groups[] = {
4227 "drif2_ctrl_a",
4228 "drif2_data0_a",
4229 "drif2_data1_a",
4230 "drif2_ctrl_b",
4231 "drif2_data0_b",
4232 "drif2_data1_b",
4233 };
4234
4235 static const char * const drif3_groups[] = {
4236 "drif3_ctrl_a",
4237 "drif3_data0_a",
4238 "drif3_data1_a",
4239 "drif3_ctrl_b",
4240 "drif3_data0_b",
4241 "drif3_data1_b",
4242 };
4243
4244 static const char * const du_groups[] = {
4245 "du_rgb666",
4246 "du_rgb888",
4247 "du_clk_out_0",
4248 "du_clk_out_1",
4249 "du_sync",
4250 "du_oddf",
4251 "du_cde",
4252 "du_disp",
4253 };
4254
4255 static const char * const hscif0_groups[] = {
4256 "hscif0_data",
4257 "hscif0_clk",
4258 "hscif0_ctrl",
4259 };
4260
4261 static const char * const hscif1_groups[] = {
4262 "hscif1_data_a",
4263 "hscif1_clk_a",
4264 "hscif1_ctrl_a",
4265 "hscif1_data_b",
4266 "hscif1_clk_b",
4267 "hscif1_ctrl_b",
4268 };
4269
4270 static const char * const hscif2_groups[] = {
4271 "hscif2_data_a",
4272 "hscif2_clk_a",
4273 "hscif2_ctrl_a",
4274 "hscif2_data_b",
4275 "hscif2_clk_b",
4276 "hscif2_ctrl_b",
4277 };
4278
4279 static const char * const hscif3_groups[] = {
4280 "hscif3_data_a",
4281 "hscif3_clk",
4282 "hscif3_ctrl",
4283 "hscif3_data_b",
4284 "hscif3_data_c",
4285 "hscif3_data_d",
4286 };
4287
4288 static const char * const hscif4_groups[] = {
4289 "hscif4_data_a",
4290 "hscif4_clk",
4291 "hscif4_ctrl",
4292 "hscif4_data_b",
4293 };
4294
4295 static const char * const i2c0_groups[] = {
4296 "i2c0",
4297 };
4298
4299 static const char * const i2c1_groups[] = {
4300 "i2c1_a",
4301 "i2c1_b",
4302 };
4303
4304 static const char * const i2c2_groups[] = {
4305 "i2c2_a",
4306 "i2c2_b",
4307 };
4308
4309 static const char * const i2c3_groups[] = {
4310 "i2c3",
4311 };
4312
4313 static const char * const i2c5_groups[] = {
4314 "i2c5",
4315 };
4316
4317 static const char * const i2c6_groups[] = {
4318 "i2c6_a",
4319 "i2c6_b",
4320 "i2c6_c",
4321 };
4322
4323 static const char * const intc_ex_groups[] = {
4324 "intc_ex_irq0",
4325 "intc_ex_irq1",
4326 "intc_ex_irq2",
4327 "intc_ex_irq3",
4328 "intc_ex_irq4",
4329 "intc_ex_irq5",
4330 };
4331
4332 static const char * const mlb_3pin_groups[] = {
4333 "mlb_3pin",
4334 };
4335
4336 static const char * const msiof0_groups[] = {
4337 "msiof0_clk",
4338 "msiof0_sync",
4339 "msiof0_ss1",
4340 "msiof0_ss2",
4341 "msiof0_txd",
4342 "msiof0_rxd",
4343 };
4344
4345 static const char * const msiof1_groups[] = {
4346 "msiof1_clk_a",
4347 "msiof1_sync_a",
4348 "msiof1_ss1_a",
4349 "msiof1_ss2_a",
4350 "msiof1_txd_a",
4351 "msiof1_rxd_a",
4352 "msiof1_clk_b",
4353 "msiof1_sync_b",
4354 "msiof1_ss1_b",
4355 "msiof1_ss2_b",
4356 "msiof1_txd_b",
4357 "msiof1_rxd_b",
4358 "msiof1_clk_c",
4359 "msiof1_sync_c",
4360 "msiof1_ss1_c",
4361 "msiof1_ss2_c",
4362 "msiof1_txd_c",
4363 "msiof1_rxd_c",
4364 "msiof1_clk_d",
4365 "msiof1_sync_d",
4366 "msiof1_ss1_d",
4367 "msiof1_ss2_d",
4368 "msiof1_txd_d",
4369 "msiof1_rxd_d",
4370 "msiof1_clk_e",
4371 "msiof1_sync_e",
4372 "msiof1_ss1_e",
4373 "msiof1_ss2_e",
4374 "msiof1_txd_e",
4375 "msiof1_rxd_e",
4376 "msiof1_clk_f",
4377 "msiof1_sync_f",
4378 "msiof1_ss1_f",
4379 "msiof1_ss2_f",
4380 "msiof1_txd_f",
4381 "msiof1_rxd_f",
4382 "msiof1_clk_g",
4383 "msiof1_sync_g",
4384 "msiof1_ss1_g",
4385 "msiof1_ss2_g",
4386 "msiof1_txd_g",
4387 "msiof1_rxd_g",
4388 };
4389
4390 static const char * const msiof2_groups[] = {
4391 "msiof2_clk_a",
4392 "msiof2_sync_a",
4393 "msiof2_ss1_a",
4394 "msiof2_ss2_a",
4395 "msiof2_txd_a",
4396 "msiof2_rxd_a",
4397 "msiof2_clk_b",
4398 "msiof2_sync_b",
4399 "msiof2_ss1_b",
4400 "msiof2_ss2_b",
4401 "msiof2_txd_b",
4402 "msiof2_rxd_b",
4403 "msiof2_clk_c",
4404 "msiof2_sync_c",
4405 "msiof2_ss1_c",
4406 "msiof2_ss2_c",
4407 "msiof2_txd_c",
4408 "msiof2_rxd_c",
4409 "msiof2_clk_d",
4410 "msiof2_sync_d",
4411 "msiof2_ss1_d",
4412 "msiof2_ss2_d",
4413 "msiof2_txd_d",
4414 "msiof2_rxd_d",
4415 };
4416
4417 static const char * const msiof3_groups[] = {
4418 "msiof3_clk_a",
4419 "msiof3_sync_a",
4420 "msiof3_ss1_a",
4421 "msiof3_ss2_a",
4422 "msiof3_txd_a",
4423 "msiof3_rxd_a",
4424 "msiof3_clk_b",
4425 "msiof3_sync_b",
4426 "msiof3_ss1_b",
4427 "msiof3_ss2_b",
4428 "msiof3_txd_b",
4429 "msiof3_rxd_b",
4430 "msiof3_clk_c",
4431 "msiof3_sync_c",
4432 "msiof3_txd_c",
4433 "msiof3_rxd_c",
4434 "msiof3_clk_d",
4435 "msiof3_sync_d",
4436 "msiof3_ss1_d",
4437 "msiof3_txd_d",
4438 "msiof3_rxd_d",
4439 };
4440
4441 static const char * const pwm0_groups[] = {
4442 "pwm0",
4443 };
4444
4445 static const char * const pwm1_groups[] = {
4446 "pwm1_a",
4447 "pwm1_b",
4448 };
4449
4450 static const char * const pwm2_groups[] = {
4451 "pwm2_a",
4452 "pwm2_b",
4453 };
4454
4455 static const char * const pwm3_groups[] = {
4456 "pwm3_a",
4457 "pwm3_b",
4458 };
4459
4460 static const char * const pwm4_groups[] = {
4461 "pwm4_a",
4462 "pwm4_b",
4463 };
4464
4465 static const char * const pwm5_groups[] = {
4466 "pwm5_a",
4467 "pwm5_b",
4468 };
4469
4470 static const char * const pwm6_groups[] = {
4471 "pwm6_a",
4472 "pwm6_b",
4473 };
4474
4475 static const char * const qspi0_groups[] = {
4476 "qspi0_ctrl",
4477 "qspi0_data2",
4478 "qspi0_data4",
4479 };
4480
4481 static const char * const qspi1_groups[] = {
4482 "qspi1_ctrl",
4483 "qspi1_data2",
4484 "qspi1_data4",
4485 };
4486
4487 static const char * const sata0_groups[] = {
4488 "sata0_devslp_a",
4489 "sata0_devslp_b",
4490 };
4491
4492 static const char * const scif0_groups[] = {
4493 "scif0_data",
4494 "scif0_clk",
4495 "scif0_ctrl",
4496 };
4497
4498 static const char * const scif1_groups[] = {
4499 "scif1_data_a",
4500 "scif1_clk",
4501 "scif1_ctrl",
4502 "scif1_data_b",
4503 };
4504
4505 static const char * const scif2_groups[] = {
4506 "scif2_data_a",
4507 "scif2_clk",
4508 "scif2_data_b",
4509 };
4510
4511 static const char * const scif3_groups[] = {
4512 "scif3_data_a",
4513 "scif3_clk",
4514 "scif3_ctrl",
4515 "scif3_data_b",
4516 };
4517
4518 static const char * const scif4_groups[] = {
4519 "scif4_data_a",
4520 "scif4_clk_a",
4521 "scif4_ctrl_a",
4522 "scif4_data_b",
4523 "scif4_clk_b",
4524 "scif4_ctrl_b",
4525 "scif4_data_c",
4526 "scif4_clk_c",
4527 "scif4_ctrl_c",
4528 };
4529
4530 static const char * const scif5_groups[] = {
4531 "scif5_data",
4532 "scif5_clk",
4533 };
4534
4535 static const char * const scif_clk_groups[] = {
4536 "scif_clk_a",
4537 "scif_clk_b",
4538 };
4539
4540 static const char * const sdhi0_groups[] = {
4541 "sdhi0_data1",
4542 "sdhi0_data4",
4543 "sdhi0_ctrl",
4544 "sdhi0_cd",
4545 "sdhi0_wp",
4546 };
4547
4548 static const char * const sdhi1_groups[] = {
4549 "sdhi1_data1",
4550 "sdhi1_data4",
4551 "sdhi1_ctrl",
4552 "sdhi1_cd",
4553 "sdhi1_wp",
4554 };
4555
4556 static const char * const sdhi2_groups[] = {
4557 "sdhi2_data1",
4558 "sdhi2_data4",
4559 "sdhi2_data8",
4560 "sdhi2_ctrl",
4561 "sdhi2_cd_a",
4562 "sdhi2_wp_a",
4563 "sdhi2_cd_b",
4564 "sdhi2_wp_b",
4565 "sdhi2_ds",
4566 };
4567
4568 static const char * const sdhi3_groups[] = {
4569 "sdhi3_data1",
4570 "sdhi3_data4",
4571 "sdhi3_data8",
4572 "sdhi3_ctrl",
4573 "sdhi3_cd",
4574 "sdhi3_wp",
4575 "sdhi3_ds",
4576 };
4577
4578 static const char * const ssi_groups[] = {
4579 "ssi0_data",
4580 "ssi01239_ctrl",
4581 "ssi1_data_a",
4582 "ssi1_data_b",
4583 "ssi1_ctrl_a",
4584 "ssi1_ctrl_b",
4585 "ssi2_data_a",
4586 "ssi2_data_b",
4587 "ssi2_ctrl_a",
4588 "ssi2_ctrl_b",
4589 "ssi3_data",
4590 "ssi349_ctrl",
4591 "ssi4_data",
4592 "ssi4_ctrl",
4593 "ssi5_data",
4594 "ssi5_ctrl",
4595 "ssi6_data",
4596 "ssi6_ctrl",
4597 "ssi7_data",
4598 "ssi78_ctrl",
4599 "ssi8_data",
4600 "ssi9_data_a",
4601 "ssi9_data_b",
4602 "ssi9_ctrl_a",
4603 "ssi9_ctrl_b",
4604 };
4605
4606 static const char * const tmu_groups[] = {
4607 "tmu_tclk1_a",
4608 "tmu_tclk1_b",
4609 "tmu_tclk2_a",
4610 "tmu_tclk2_b",
4611 };
4612
4613 static const char * const tpu_groups[] = {
4614 "tpu_to0",
4615 "tpu_to1",
4616 "tpu_to2",
4617 "tpu_to3",
4618 };
4619
4620 static const char * const usb0_groups[] = {
4621 "usb0",
4622 };
4623
4624 static const char * const usb1_groups[] = {
4625 "usb1",
4626 };
4627
4628 static const char * const usb2_groups[] = {
4629 "usb2",
4630 };
4631
4632 static const char * const usb30_groups[] = {
4633 "usb30",
4634 };
4635
4636 static const char * const usb31_groups[] = {
4637 "usb31",
4638 };
4639
4640 static const struct sh_pfc_function pinmux_functions[] = {
4641 SH_PFC_FUNCTION(audio_clk),
4642 SH_PFC_FUNCTION(avb),
4643 SH_PFC_FUNCTION(can0),
4644 SH_PFC_FUNCTION(can1),
4645 SH_PFC_FUNCTION(can_clk),
4646 SH_PFC_FUNCTION(canfd0),
4647 SH_PFC_FUNCTION(canfd1),
4648 SH_PFC_FUNCTION(drif0),
4649 SH_PFC_FUNCTION(drif1),
4650 SH_PFC_FUNCTION(drif2),
4651 SH_PFC_FUNCTION(drif3),
4652 SH_PFC_FUNCTION(du),
4653 SH_PFC_FUNCTION(hscif0),
4654 SH_PFC_FUNCTION(hscif1),
4655 SH_PFC_FUNCTION(hscif2),
4656 SH_PFC_FUNCTION(hscif3),
4657 SH_PFC_FUNCTION(hscif4),
4658 SH_PFC_FUNCTION(i2c0),
4659 SH_PFC_FUNCTION(i2c1),
4660 SH_PFC_FUNCTION(i2c2),
4661 SH_PFC_FUNCTION(i2c3),
4662 SH_PFC_FUNCTION(i2c5),
4663 SH_PFC_FUNCTION(i2c6),
4664 SH_PFC_FUNCTION(intc_ex),
4665 SH_PFC_FUNCTION(mlb_3pin),
4666 SH_PFC_FUNCTION(msiof0),
4667 SH_PFC_FUNCTION(msiof1),
4668 SH_PFC_FUNCTION(msiof2),
4669 SH_PFC_FUNCTION(msiof3),
4670 SH_PFC_FUNCTION(pwm0),
4671 SH_PFC_FUNCTION(pwm1),
4672 SH_PFC_FUNCTION(pwm2),
4673 SH_PFC_FUNCTION(pwm3),
4674 SH_PFC_FUNCTION(pwm4),
4675 SH_PFC_FUNCTION(pwm5),
4676 SH_PFC_FUNCTION(pwm6),
4677 SH_PFC_FUNCTION(qspi0),
4678 SH_PFC_FUNCTION(qspi1),
4679 SH_PFC_FUNCTION(sata0),
4680 SH_PFC_FUNCTION(scif0),
4681 SH_PFC_FUNCTION(scif1),
4682 SH_PFC_FUNCTION(scif2),
4683 SH_PFC_FUNCTION(scif3),
4684 SH_PFC_FUNCTION(scif4),
4685 SH_PFC_FUNCTION(scif5),
4686 SH_PFC_FUNCTION(scif_clk),
4687 SH_PFC_FUNCTION(sdhi0),
4688 SH_PFC_FUNCTION(sdhi1),
4689 SH_PFC_FUNCTION(sdhi2),
4690 SH_PFC_FUNCTION(sdhi3),
4691 SH_PFC_FUNCTION(ssi),
4692 SH_PFC_FUNCTION(tmu),
4693 SH_PFC_FUNCTION(tpu),
4694 SH_PFC_FUNCTION(usb0),
4695 SH_PFC_FUNCTION(usb1),
4696 SH_PFC_FUNCTION(usb2),
4697 SH_PFC_FUNCTION(usb30),
4698 SH_PFC_FUNCTION(usb31),
4699 };
4700
4701 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4702 #define F_(x, y) FN_##y
4703 #define FM(x) FN_##x
4704 { PINMUX_CFG_REG_VAR("GPSR0", 0xe6060100, 32,
4705 GROUP(-16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
4706 1, 1, 1, 1, 1),
4707 GROUP(
4708 /* GP0_31_16 RESERVED */
4709 GP_0_15_FN, GPSR0_15,
4710 GP_0_14_FN, GPSR0_14,
4711 GP_0_13_FN, GPSR0_13,
4712 GP_0_12_FN, GPSR0_12,
4713 GP_0_11_FN, GPSR0_11,
4714 GP_0_10_FN, GPSR0_10,
4715 GP_0_9_FN, GPSR0_9,
4716 GP_0_8_FN, GPSR0_8,
4717 GP_0_7_FN, GPSR0_7,
4718 GP_0_6_FN, GPSR0_6,
4719 GP_0_5_FN, GPSR0_5,
4720 GP_0_4_FN, GPSR0_4,
4721 GP_0_3_FN, GPSR0_3,
4722 GP_0_2_FN, GPSR0_2,
4723 GP_0_1_FN, GPSR0_1,
4724 GP_0_0_FN, GPSR0_0, ))
4725 },
4726 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
4727 0, 0,
4728 0, 0,
4729 0, 0,
4730 0, 0,
4731 GP_1_27_FN, GPSR1_27,
4732 GP_1_26_FN, GPSR1_26,
4733 GP_1_25_FN, GPSR1_25,
4734 GP_1_24_FN, GPSR1_24,
4735 GP_1_23_FN, GPSR1_23,
4736 GP_1_22_FN, GPSR1_22,
4737 GP_1_21_FN, GPSR1_21,
4738 GP_1_20_FN, GPSR1_20,
4739 GP_1_19_FN, GPSR1_19,
4740 GP_1_18_FN, GPSR1_18,
4741 GP_1_17_FN, GPSR1_17,
4742 GP_1_16_FN, GPSR1_16,
4743 GP_1_15_FN, GPSR1_15,
4744 GP_1_14_FN, GPSR1_14,
4745 GP_1_13_FN, GPSR1_13,
4746 GP_1_12_FN, GPSR1_12,
4747 GP_1_11_FN, GPSR1_11,
4748 GP_1_10_FN, GPSR1_10,
4749 GP_1_9_FN, GPSR1_9,
4750 GP_1_8_FN, GPSR1_8,
4751 GP_1_7_FN, GPSR1_7,
4752 GP_1_6_FN, GPSR1_6,
4753 GP_1_5_FN, GPSR1_5,
4754 GP_1_4_FN, GPSR1_4,
4755 GP_1_3_FN, GPSR1_3,
4756 GP_1_2_FN, GPSR1_2,
4757 GP_1_1_FN, GPSR1_1,
4758 GP_1_0_FN, GPSR1_0, ))
4759 },
4760 { PINMUX_CFG_REG_VAR("GPSR2", 0xe6060108, 32,
4761 GROUP(-17, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
4762 1, 1, 1, 1),
4763 GROUP(
4764 /* GP2_31_15 RESERVED */
4765 GP_2_14_FN, GPSR2_14,
4766 GP_2_13_FN, GPSR2_13,
4767 GP_2_12_FN, GPSR2_12,
4768 GP_2_11_FN, GPSR2_11,
4769 GP_2_10_FN, GPSR2_10,
4770 GP_2_9_FN, GPSR2_9,
4771 GP_2_8_FN, GPSR2_8,
4772 GP_2_7_FN, GPSR2_7,
4773 GP_2_6_FN, GPSR2_6,
4774 GP_2_5_FN, GPSR2_5,
4775 GP_2_4_FN, GPSR2_4,
4776 GP_2_3_FN, GPSR2_3,
4777 GP_2_2_FN, GPSR2_2,
4778 GP_2_1_FN, GPSR2_1,
4779 GP_2_0_FN, GPSR2_0, ))
4780 },
4781 { PINMUX_CFG_REG_VAR("GPSR3", 0xe606010c, 32,
4782 GROUP(-16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
4783 1, 1, 1, 1, 1),
4784 GROUP(
4785 /* GP3_31_16 RESERVED */
4786 GP_3_15_FN, GPSR3_15,
4787 GP_3_14_FN, GPSR3_14,
4788 GP_3_13_FN, GPSR3_13,
4789 GP_3_12_FN, GPSR3_12,
4790 GP_3_11_FN, GPSR3_11,
4791 GP_3_10_FN, GPSR3_10,
4792 GP_3_9_FN, GPSR3_9,
4793 GP_3_8_FN, GPSR3_8,
4794 GP_3_7_FN, GPSR3_7,
4795 GP_3_6_FN, GPSR3_6,
4796 GP_3_5_FN, GPSR3_5,
4797 GP_3_4_FN, GPSR3_4,
4798 GP_3_3_FN, GPSR3_3,
4799 GP_3_2_FN, GPSR3_2,
4800 GP_3_1_FN, GPSR3_1,
4801 GP_3_0_FN, GPSR3_0, ))
4802 },
4803 { PINMUX_CFG_REG_VAR("GPSR4", 0xe6060110, 32,
4804 GROUP(-14, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
4805 1, 1, 1, 1, 1, 1, 1),
4806 GROUP(
4807 /* GP4_31_18 RESERVED */
4808 GP_4_17_FN, GPSR4_17,
4809 GP_4_16_FN, GPSR4_16,
4810 GP_4_15_FN, GPSR4_15,
4811 GP_4_14_FN, GPSR4_14,
4812 GP_4_13_FN, GPSR4_13,
4813 GP_4_12_FN, GPSR4_12,
4814 GP_4_11_FN, GPSR4_11,
4815 GP_4_10_FN, GPSR4_10,
4816 GP_4_9_FN, GPSR4_9,
4817 GP_4_8_FN, GPSR4_8,
4818 GP_4_7_FN, GPSR4_7,
4819 GP_4_6_FN, GPSR4_6,
4820 GP_4_5_FN, GPSR4_5,
4821 GP_4_4_FN, GPSR4_4,
4822 GP_4_3_FN, GPSR4_3,
4823 GP_4_2_FN, GPSR4_2,
4824 GP_4_1_FN, GPSR4_1,
4825 GP_4_0_FN, GPSR4_0, ))
4826 },
4827 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
4828 0, 0,
4829 0, 0,
4830 0, 0,
4831 0, 0,
4832 0, 0,
4833 0, 0,
4834 GP_5_25_FN, GPSR5_25,
4835 GP_5_24_FN, GPSR5_24,
4836 GP_5_23_FN, GPSR5_23,
4837 GP_5_22_FN, GPSR5_22,
4838 GP_5_21_FN, GPSR5_21,
4839 GP_5_20_FN, GPSR5_20,
4840 GP_5_19_FN, GPSR5_19,
4841 GP_5_18_FN, GPSR5_18,
4842 GP_5_17_FN, GPSR5_17,
4843 GP_5_16_FN, GPSR5_16,
4844 GP_5_15_FN, GPSR5_15,
4845 GP_5_14_FN, GPSR5_14,
4846 GP_5_13_FN, GPSR5_13,
4847 GP_5_12_FN, GPSR5_12,
4848 GP_5_11_FN, GPSR5_11,
4849 GP_5_10_FN, GPSR5_10,
4850 GP_5_9_FN, GPSR5_9,
4851 GP_5_8_FN, GPSR5_8,
4852 GP_5_7_FN, GPSR5_7,
4853 GP_5_6_FN, GPSR5_6,
4854 GP_5_5_FN, GPSR5_5,
4855 GP_5_4_FN, GPSR5_4,
4856 GP_5_3_FN, GPSR5_3,
4857 GP_5_2_FN, GPSR5_2,
4858 GP_5_1_FN, GPSR5_1,
4859 GP_5_0_FN, GPSR5_0, ))
4860 },
4861 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP(
4862 GP_6_31_FN, GPSR6_31,
4863 GP_6_30_FN, GPSR6_30,
4864 GP_6_29_FN, GPSR6_29,
4865 GP_6_28_FN, GPSR6_28,
4866 GP_6_27_FN, GPSR6_27,
4867 GP_6_26_FN, GPSR6_26,
4868 GP_6_25_FN, GPSR6_25,
4869 GP_6_24_FN, GPSR6_24,
4870 GP_6_23_FN, GPSR6_23,
4871 GP_6_22_FN, GPSR6_22,
4872 GP_6_21_FN, GPSR6_21,
4873 GP_6_20_FN, GPSR6_20,
4874 GP_6_19_FN, GPSR6_19,
4875 GP_6_18_FN, GPSR6_18,
4876 GP_6_17_FN, GPSR6_17,
4877 GP_6_16_FN, GPSR6_16,
4878 GP_6_15_FN, GPSR6_15,
4879 GP_6_14_FN, GPSR6_14,
4880 GP_6_13_FN, GPSR6_13,
4881 GP_6_12_FN, GPSR6_12,
4882 GP_6_11_FN, GPSR6_11,
4883 GP_6_10_FN, GPSR6_10,
4884 GP_6_9_FN, GPSR6_9,
4885 GP_6_8_FN, GPSR6_8,
4886 GP_6_7_FN, GPSR6_7,
4887 GP_6_6_FN, GPSR6_6,
4888 GP_6_5_FN, GPSR6_5,
4889 GP_6_4_FN, GPSR6_4,
4890 GP_6_3_FN, GPSR6_3,
4891 GP_6_2_FN, GPSR6_2,
4892 GP_6_1_FN, GPSR6_1,
4893 GP_6_0_FN, GPSR6_0, ))
4894 },
4895 { PINMUX_CFG_REG_VAR("GPSR7", 0xe606011c, 32,
4896 GROUP(-28, 1, 1, 1, 1),
4897 GROUP(
4898 /* GP7_31_4 RESERVED */
4899 GP_7_3_FN, GPSR7_3,
4900 GP_7_2_FN, GPSR7_2,
4901 GP_7_1_FN, GPSR7_1,
4902 GP_7_0_FN, GPSR7_0, ))
4903 },
4904 #undef F_
4905 #undef FM
4906
4907 #define F_(x, y) x,
4908 #define FM(x) FN_##x,
4909 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
4910 IP0_31_28
4911 IP0_27_24
4912 IP0_23_20
4913 IP0_19_16
4914 IP0_15_12
4915 IP0_11_8
4916 IP0_7_4
4917 IP0_3_0 ))
4918 },
4919 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
4920 IP1_31_28
4921 IP1_27_24
4922 IP1_23_20
4923 IP1_19_16
4924 IP1_15_12
4925 IP1_11_8
4926 IP1_7_4
4927 IP1_3_0 ))
4928 },
4929 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
4930 IP2_31_28
4931 IP2_27_24
4932 IP2_23_20
4933 IP2_19_16
4934 IP2_15_12
4935 IP2_11_8
4936 IP2_7_4
4937 IP2_3_0 ))
4938 },
4939 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
4940 IP3_31_28
4941 IP3_27_24
4942 IP3_23_20
4943 IP3_19_16
4944 IP3_15_12
4945 IP3_11_8
4946 IP3_7_4
4947 IP3_3_0 ))
4948 },
4949 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
4950 IP4_31_28
4951 IP4_27_24
4952 IP4_23_20
4953 IP4_19_16
4954 IP4_15_12
4955 IP4_11_8
4956 IP4_7_4
4957 IP4_3_0 ))
4958 },
4959 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
4960 IP5_31_28
4961 IP5_27_24
4962 IP5_23_20
4963 IP5_19_16
4964 IP5_15_12
4965 IP5_11_8
4966 IP5_7_4
4967 IP5_3_0 ))
4968 },
4969 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
4970 IP6_31_28
4971 IP6_27_24
4972 IP6_23_20
4973 IP6_19_16
4974 IP6_15_12
4975 IP6_11_8
4976 IP6_7_4
4977 IP6_3_0 ))
4978 },
4979 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
4980 IP7_31_28
4981 IP7_27_24
4982 IP7_23_20
4983 IP7_19_16
4984 IP7_15_12
4985 IP7_11_8
4986 IP7_7_4
4987 IP7_3_0 ))
4988 },
4989 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
4990 IP8_31_28
4991 IP8_27_24
4992 IP8_23_20
4993 IP8_19_16
4994 IP8_15_12
4995 IP8_11_8
4996 IP8_7_4
4997 IP8_3_0 ))
4998 },
4999 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
5000 IP9_31_28
5001 IP9_27_24
5002 IP9_23_20
5003 IP9_19_16
5004 IP9_15_12
5005 IP9_11_8
5006 IP9_7_4
5007 IP9_3_0 ))
5008 },
5009 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP(
5010 IP10_31_28
5011 IP10_27_24
5012 IP10_23_20
5013 IP10_19_16
5014 IP10_15_12
5015 IP10_11_8
5016 IP10_7_4
5017 IP10_3_0 ))
5018 },
5019 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP(
5020 IP11_31_28
5021 IP11_27_24
5022 IP11_23_20
5023 IP11_19_16
5024 IP11_15_12
5025 IP11_11_8
5026 IP11_7_4
5027 IP11_3_0 ))
5028 },
5029 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP(
5030 IP12_31_28
5031 IP12_27_24
5032 IP12_23_20
5033 IP12_19_16
5034 IP12_15_12
5035 IP12_11_8
5036 IP12_7_4
5037 IP12_3_0 ))
5038 },
5039 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP(
5040 IP13_31_28
5041 IP13_27_24
5042 IP13_23_20
5043 IP13_19_16
5044 IP13_15_12
5045 IP13_11_8
5046 IP13_7_4
5047 IP13_3_0 ))
5048 },
5049 { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4, GROUP(
5050 IP14_31_28
5051 IP14_27_24
5052 IP14_23_20
5053 IP14_19_16
5054 IP14_15_12
5055 IP14_11_8
5056 IP14_7_4
5057 IP14_3_0 ))
5058 },
5059 { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4, GROUP(
5060 IP15_31_28
5061 IP15_27_24
5062 IP15_23_20
5063 IP15_19_16
5064 IP15_15_12
5065 IP15_11_8
5066 IP15_7_4
5067 IP15_3_0 ))
5068 },
5069 { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4, GROUP(
5070 IP16_31_28
5071 IP16_27_24
5072 IP16_23_20
5073 IP16_19_16
5074 IP16_15_12
5075 IP16_11_8
5076 IP16_7_4
5077 IP16_3_0 ))
5078 },
5079 { PINMUX_CFG_REG_VAR("IPSR17", 0xe6060244, 32,
5080 GROUP(-24, 4, 4),
5081 GROUP(
5082 /* IP17_31_8 RESERVED */
5083 IP17_7_4
5084 IP17_3_0 ))
5085 },
5086 #undef F_
5087 #undef FM
5088
5089 #define F_(x, y) x,
5090 #define FM(x) FN_##x,
5091 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
5092 GROUP(-1, 2, 2, 3, 1, 1, 2, 1, 1, 1, 2, 1,
5093 1, 1, 1, 1, 1, 1, 2, 2, 1, 2, -1),
5094 GROUP(
5095 /* RESERVED 31 */
5096 MOD_SEL0_30_29
5097 MOD_SEL0_28_27
5098 MOD_SEL0_26_25_24
5099 MOD_SEL0_23
5100 MOD_SEL0_22
5101 MOD_SEL0_21_20
5102 MOD_SEL0_19
5103 MOD_SEL0_18
5104 MOD_SEL0_17
5105 MOD_SEL0_16_15
5106 MOD_SEL0_14
5107 MOD_SEL0_13
5108 MOD_SEL0_12
5109 MOD_SEL0_11
5110 MOD_SEL0_10
5111 MOD_SEL0_9
5112 MOD_SEL0_8
5113 MOD_SEL0_7_6
5114 MOD_SEL0_5_4
5115 MOD_SEL0_3
5116 MOD_SEL0_2_1
5117 /* RESERVED 0 */ ))
5118 },
5119 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
5120 GROUP(2, 3, 1, 2, 3, 1, 1, 2, 1, 2, 1, 1,
5121 1, 1, 1, -2, 1, 1, 1, 1, 1, 1, 1),
5122 GROUP(
5123 MOD_SEL1_31_30
5124 MOD_SEL1_29_28_27
5125 MOD_SEL1_26
5126 MOD_SEL1_25_24
5127 MOD_SEL1_23_22_21
5128 MOD_SEL1_20
5129 MOD_SEL1_19
5130 MOD_SEL1_18_17
5131 MOD_SEL1_16
5132 MOD_SEL1_15_14
5133 MOD_SEL1_13
5134 MOD_SEL1_12
5135 MOD_SEL1_11
5136 MOD_SEL1_10
5137 MOD_SEL1_9
5138 /* RESERVED 8, 7 */
5139 MOD_SEL1_6
5140 MOD_SEL1_5
5141 MOD_SEL1_4
5142 MOD_SEL1_3
5143 MOD_SEL1_2
5144 MOD_SEL1_1
5145 MOD_SEL1_0 ))
5146 },
5147 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
5148 GROUP(1, 1, 1, -28, 1),
5149 GROUP(
5150 MOD_SEL2_31
5151 MOD_SEL2_30
5152 MOD_SEL2_29
5153 /* RESERVED 28-1 */
5154 MOD_SEL2_0 ))
5155 },
5156 { },
5157 };
5158
5159 static const struct pinmux_drive_reg pinmux_drive_regs[] = {
5160 { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
5161 { PIN_QSPI0_SPCLK, 28, 2 }, /* QSPI0_SPCLK */
5162 { PIN_QSPI0_MOSI_IO0, 24, 2 }, /* QSPI0_MOSI_IO0 */
5163 { PIN_QSPI0_MISO_IO1, 20, 2 }, /* QSPI0_MISO_IO1 */
5164 { PIN_QSPI0_IO2, 16, 2 }, /* QSPI0_IO2 */
5165 { PIN_QSPI0_IO3, 12, 2 }, /* QSPI0_IO3 */
5166 { PIN_QSPI0_SSL, 8, 2 }, /* QSPI0_SSL */
5167 { PIN_QSPI1_SPCLK, 4, 2 }, /* QSPI1_SPCLK */
5168 { PIN_QSPI1_MOSI_IO0, 0, 2 }, /* QSPI1_MOSI_IO0 */
5169 } },
5170 { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
5171 { PIN_QSPI1_MISO_IO1, 28, 2 }, /* QSPI1_MISO_IO1 */
5172 { PIN_QSPI1_IO2, 24, 2 }, /* QSPI1_IO2 */
5173 { PIN_QSPI1_IO3, 20, 2 }, /* QSPI1_IO3 */
5174 { PIN_QSPI1_SSL, 16, 2 }, /* QSPI1_SSL */
5175 { PIN_RPC_INT_N, 12, 2 }, /* RPC_INT# */
5176 { PIN_RPC_WP_N, 8, 2 }, /* RPC_WP# */
5177 { PIN_RPC_RESET_N, 4, 2 }, /* RPC_RESET# */
5178 { PIN_AVB_RX_CTL, 0, 3 }, /* AVB_RX_CTL */
5179 } },
5180 { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
5181 { PIN_AVB_RXC, 28, 3 }, /* AVB_RXC */
5182 { PIN_AVB_RD0, 24, 3 }, /* AVB_RD0 */
5183 { PIN_AVB_RD1, 20, 3 }, /* AVB_RD1 */
5184 { PIN_AVB_RD2, 16, 3 }, /* AVB_RD2 */
5185 { PIN_AVB_RD3, 12, 3 }, /* AVB_RD3 */
5186 { PIN_AVB_TX_CTL, 8, 3 }, /* AVB_TX_CTL */
5187 { PIN_AVB_TXC, 4, 3 }, /* AVB_TXC */
5188 { PIN_AVB_TD0, 0, 3 }, /* AVB_TD0 */
5189 } },
5190 { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
5191 { PIN_AVB_TD1, 28, 3 }, /* AVB_TD1 */
5192 { PIN_AVB_TD2, 24, 3 }, /* AVB_TD2 */
5193 { PIN_AVB_TD3, 20, 3 }, /* AVB_TD3 */
5194 { PIN_AVB_TXCREFCLK, 16, 3 }, /* AVB_TXCREFCLK */
5195 { PIN_AVB_MDIO, 12, 3 }, /* AVB_MDIO */
5196 { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
5197 { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
5198 { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
5199 } },
5200 { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
5201 { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */
5202 { RCAR_GP_PIN(2, 13), 24, 3 }, /* AVB_AVTP_MATCH */
5203 { RCAR_GP_PIN(2, 14), 20, 3 }, /* AVB_AVTP_CAPTURE */
5204 { RCAR_GP_PIN(2, 0), 16, 3 }, /* IRQ0 */
5205 { RCAR_GP_PIN(2, 1), 12, 3 }, /* IRQ1 */
5206 { RCAR_GP_PIN(2, 2), 8, 3 }, /* IRQ2 */
5207 { RCAR_GP_PIN(2, 3), 4, 3 }, /* IRQ3 */
5208 { RCAR_GP_PIN(2, 4), 0, 3 }, /* IRQ4 */
5209 } },
5210 { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) {
5211 { RCAR_GP_PIN(2, 5), 28, 3 }, /* IRQ5 */
5212 { RCAR_GP_PIN(2, 6), 24, 3 }, /* PWM0 */
5213 { RCAR_GP_PIN(2, 7), 20, 3 }, /* PWM1 */
5214 { RCAR_GP_PIN(2, 8), 16, 3 }, /* PWM2 */
5215 { RCAR_GP_PIN(1, 0), 12, 3 }, /* A0 */
5216 { RCAR_GP_PIN(1, 1), 8, 3 }, /* A1 */
5217 { RCAR_GP_PIN(1, 2), 4, 3 }, /* A2 */
5218 { RCAR_GP_PIN(1, 3), 0, 3 }, /* A3 */
5219 } },
5220 { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) {
5221 { RCAR_GP_PIN(1, 4), 28, 3 }, /* A4 */
5222 { RCAR_GP_PIN(1, 5), 24, 3 }, /* A5 */
5223 { RCAR_GP_PIN(1, 6), 20, 3 }, /* A6 */
5224 { RCAR_GP_PIN(1, 7), 16, 3 }, /* A7 */
5225 { RCAR_GP_PIN(1, 8), 12, 3 }, /* A8 */
5226 { RCAR_GP_PIN(1, 9), 8, 3 }, /* A9 */
5227 { RCAR_GP_PIN(1, 10), 4, 3 }, /* A10 */
5228 { RCAR_GP_PIN(1, 11), 0, 3 }, /* A11 */
5229 } },
5230 { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) {
5231 { RCAR_GP_PIN(1, 12), 28, 3 }, /* A12 */
5232 { RCAR_GP_PIN(1, 13), 24, 3 }, /* A13 */
5233 { RCAR_GP_PIN(1, 14), 20, 3 }, /* A14 */
5234 { RCAR_GP_PIN(1, 15), 16, 3 }, /* A15 */
5235 { RCAR_GP_PIN(1, 16), 12, 3 }, /* A16 */
5236 { RCAR_GP_PIN(1, 17), 8, 3 }, /* A17 */
5237 { RCAR_GP_PIN(1, 18), 4, 3 }, /* A18 */
5238 { RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */
5239 } },
5240 { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
5241 { PIN_CLKOUT, 28, 3 }, /* CLKOUT */
5242 { RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */
5243 { RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */
5244 { RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */
5245 { RCAR_GP_PIN(1, 23), 12, 3 }, /* RD */
5246 { RCAR_GP_PIN(1, 24), 8, 3 }, /* RD_WR */
5247 { RCAR_GP_PIN(1, 25), 4, 3 }, /* WE0 */
5248 { RCAR_GP_PIN(1, 26), 0, 3 }, /* WE1 */
5249 } },
5250 { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
5251 { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */
5252 { PIN_PRESETOUT_N, 24, 3 }, /* PRESETOUT# */
5253 { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */
5254 { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */
5255 { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */
5256 { RCAR_GP_PIN(0, 3), 8, 3 }, /* D3 */
5257 { RCAR_GP_PIN(0, 4), 4, 3 }, /* D4 */
5258 { RCAR_GP_PIN(0, 5), 0, 3 }, /* D5 */
5259 } },
5260 { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) {
5261 { RCAR_GP_PIN(0, 6), 28, 3 }, /* D6 */
5262 { RCAR_GP_PIN(0, 7), 24, 3 }, /* D7 */
5263 { RCAR_GP_PIN(0, 8), 20, 3 }, /* D8 */
5264 { RCAR_GP_PIN(0, 9), 16, 3 }, /* D9 */
5265 { RCAR_GP_PIN(0, 10), 12, 3 }, /* D10 */
5266 { RCAR_GP_PIN(0, 11), 8, 3 }, /* D11 */
5267 { RCAR_GP_PIN(0, 12), 4, 3 }, /* D12 */
5268 { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */
5269 } },
5270 { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
5271 { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
5272 { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
5273 { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
5274 { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
5275 { RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */
5276 { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */
5277 { PIN_DU_DOTCLKIN0, 4, 2 }, /* DU_DOTCLKIN0 */
5278 { PIN_DU_DOTCLKIN1, 0, 2 }, /* DU_DOTCLKIN1 */
5279 } },
5280 { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
5281 { PIN_DU_DOTCLKIN2, 28, 2 }, /* DU_DOTCLKIN2 */
5282 { PIN_DU_DOTCLKIN3, 24, 2 }, /* DU_DOTCLKIN3 */
5283 { PIN_FSCLKST_N, 20, 2 }, /* FSCLKST# */
5284 { PIN_TMS, 4, 2 }, /* TMS */
5285 } },
5286 { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
5287 { PIN_TDO, 28, 2 }, /* TDO */
5288 { PIN_ASEBRK, 24, 2 }, /* ASEBRK */
5289 { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
5290 { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
5291 { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
5292 { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
5293 { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
5294 { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
5295 } },
5296 { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
5297 { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */
5298 { RCAR_GP_PIN(3, 7), 24, 3 }, /* SD1_CMD */
5299 { RCAR_GP_PIN(3, 8), 20, 3 }, /* SD1_DAT0 */
5300 { RCAR_GP_PIN(3, 9), 16, 3 }, /* SD1_DAT1 */
5301 { RCAR_GP_PIN(3, 10), 12, 3 }, /* SD1_DAT2 */
5302 { RCAR_GP_PIN(3, 11), 8, 3 }, /* SD1_DAT3 */
5303 { RCAR_GP_PIN(4, 0), 4, 3 }, /* SD2_CLK */
5304 { RCAR_GP_PIN(4, 1), 0, 3 }, /* SD2_CMD */
5305 } },
5306 { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) {
5307 { RCAR_GP_PIN(4, 2), 28, 3 }, /* SD2_DAT0 */
5308 { RCAR_GP_PIN(4, 3), 24, 3 }, /* SD2_DAT1 */
5309 { RCAR_GP_PIN(4, 4), 20, 3 }, /* SD2_DAT2 */
5310 { RCAR_GP_PIN(4, 5), 16, 3 }, /* SD2_DAT3 */
5311 { RCAR_GP_PIN(4, 6), 12, 3 }, /* SD2_DS */
5312 { RCAR_GP_PIN(4, 7), 8, 3 }, /* SD3_CLK */
5313 { RCAR_GP_PIN(4, 8), 4, 3 }, /* SD3_CMD */
5314 { RCAR_GP_PIN(4, 9), 0, 3 }, /* SD3_DAT0 */
5315 } },
5316 { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) {
5317 { RCAR_GP_PIN(4, 10), 28, 3 }, /* SD3_DAT1 */
5318 { RCAR_GP_PIN(4, 11), 24, 3 }, /* SD3_DAT2 */
5319 { RCAR_GP_PIN(4, 12), 20, 3 }, /* SD3_DAT3 */
5320 { RCAR_GP_PIN(4, 13), 16, 3 }, /* SD3_DAT4 */
5321 { RCAR_GP_PIN(4, 14), 12, 3 }, /* SD3_DAT5 */
5322 { RCAR_GP_PIN(4, 15), 8, 3 }, /* SD3_DAT6 */
5323 { RCAR_GP_PIN(4, 16), 4, 3 }, /* SD3_DAT7 */
5324 { RCAR_GP_PIN(4, 17), 0, 3 }, /* SD3_DS */
5325 } },
5326 { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) {
5327 { RCAR_GP_PIN(3, 12), 28, 3 }, /* SD0_CD */
5328 { RCAR_GP_PIN(3, 13), 24, 3 }, /* SD0_WP */
5329 { RCAR_GP_PIN(3, 14), 20, 3 }, /* SD1_CD */
5330 { RCAR_GP_PIN(3, 15), 16, 3 }, /* SD1_WP */
5331 { RCAR_GP_PIN(5, 0), 12, 3 }, /* SCK0 */
5332 { RCAR_GP_PIN(5, 1), 8, 3 }, /* RX0 */
5333 { RCAR_GP_PIN(5, 2), 4, 3 }, /* TX0 */
5334 { RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */
5335 } },
5336 { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
5337 { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0 */
5338 { RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */
5339 { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */
5340 { RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */
5341 { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1 */
5342 { RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */
5343 { RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */
5344 { RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */
5345 } },
5346 { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) {
5347 { RCAR_GP_PIN(5, 12), 28, 3 }, /* HSCK0 */
5348 { RCAR_GP_PIN(5, 13), 24, 3 }, /* HRX0 */
5349 { RCAR_GP_PIN(5, 14), 20, 3 }, /* HTX0 */
5350 { RCAR_GP_PIN(5, 15), 16, 3 }, /* HCTS0 */
5351 { RCAR_GP_PIN(5, 16), 12, 3 }, /* HRTS0 */
5352 { RCAR_GP_PIN(5, 17), 8, 3 }, /* MSIOF0_SCK */
5353 { RCAR_GP_PIN(5, 18), 4, 3 }, /* MSIOF0_SYNC */
5354 { RCAR_GP_PIN(5, 19), 0, 3 }, /* MSIOF0_SS1 */
5355 } },
5356 { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) {
5357 { RCAR_GP_PIN(5, 20), 28, 3 }, /* MSIOF0_TXD */
5358 { RCAR_GP_PIN(5, 21), 24, 3 }, /* MSIOF0_SS2 */
5359 { RCAR_GP_PIN(5, 22), 20, 3 }, /* MSIOF0_RXD */
5360 { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */
5361 { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */
5362 { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */
5363 { PIN_MLB_REF, 4, 3 }, /* MLB_REF */
5364 { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */
5365 } },
5366 { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
5367 { RCAR_GP_PIN(6, 1), 28, 3 }, /* SSI_WS01239 */
5368 { RCAR_GP_PIN(6, 2), 24, 3 }, /* SSI_SDATA0 */
5369 { RCAR_GP_PIN(6, 3), 20, 3 }, /* SSI_SDATA1 */
5370 { RCAR_GP_PIN(6, 4), 16, 3 }, /* SSI_SDATA2 */
5371 { RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK349 */
5372 { RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS349 */
5373 { RCAR_GP_PIN(6, 7), 4, 3 }, /* SSI_SDATA3 */
5374 { RCAR_GP_PIN(6, 8), 0, 3 }, /* SSI_SCK4 */
5375 } },
5376 { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) {
5377 { RCAR_GP_PIN(6, 9), 28, 3 }, /* SSI_WS4 */
5378 { RCAR_GP_PIN(6, 10), 24, 3 }, /* SSI_SDATA4 */
5379 { RCAR_GP_PIN(6, 11), 20, 3 }, /* SSI_SCK5 */
5380 { RCAR_GP_PIN(6, 12), 16, 3 }, /* SSI_WS5 */
5381 { RCAR_GP_PIN(6, 13), 12, 3 }, /* SSI_SDATA5 */
5382 { RCAR_GP_PIN(6, 14), 8, 3 }, /* SSI_SCK6 */
5383 { RCAR_GP_PIN(6, 15), 4, 3 }, /* SSI_WS6 */
5384 { RCAR_GP_PIN(6, 16), 0, 3 }, /* SSI_SDATA6 */
5385 } },
5386 { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) {
5387 { RCAR_GP_PIN(6, 17), 28, 3 }, /* SSI_SCK78 */
5388 { RCAR_GP_PIN(6, 18), 24, 3 }, /* SSI_WS78 */
5389 { RCAR_GP_PIN(6, 19), 20, 3 }, /* SSI_SDATA7 */
5390 { RCAR_GP_PIN(6, 20), 16, 3 }, /* SSI_SDATA8 */
5391 { RCAR_GP_PIN(6, 21), 12, 3 }, /* SSI_SDATA9 */
5392 { RCAR_GP_PIN(6, 22), 8, 3 }, /* AUDIO_CLKA */
5393 { RCAR_GP_PIN(6, 23), 4, 3 }, /* AUDIO_CLKB */
5394 { RCAR_GP_PIN(6, 24), 0, 3 }, /* USB0_PWEN */
5395 } },
5396 { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) {
5397 { RCAR_GP_PIN(6, 25), 28, 3 }, /* USB0_OVC */
5398 { RCAR_GP_PIN(6, 26), 24, 3 }, /* USB1_PWEN */
5399 { RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */
5400 { RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */
5401 { RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */
5402 { RCAR_GP_PIN(6, 30), 8, 3 }, /* USB31_PWEN */
5403 { RCAR_GP_PIN(6, 31), 4, 3 }, /* USB31_OVC */
5404 } },
5405 { },
5406 };
5407
5408 enum ioctrl_regs {
5409 POCCTRL,
5410 TDSELCTRL,
5411 };
5412
5413 static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
5414 [POCCTRL] = { 0xe6060380, },
5415 [TDSELCTRL] = { 0xe60603c0, },
5416 { /* sentinel */ },
5417 };
5418
r8a77950_pin_to_pocctrl(unsigned int pin,u32 * pocctrl)5419 static int r8a77950_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
5420 {
5421 int bit = -EINVAL;
5422
5423 *pocctrl = pinmux_ioctrl_regs[POCCTRL].reg;
5424
5425 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
5426 bit = pin & 0x1f;
5427
5428 if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
5429 bit = (pin & 0x1f) + 12;
5430
5431 return bit;
5432 }
5433
5434 static const struct pinmux_bias_reg pinmux_bias_regs[] = {
5435 { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
5436 [ 0] = PIN_QSPI0_SPCLK, /* QSPI0_SPCLK */
5437 [ 1] = PIN_QSPI0_MOSI_IO0, /* QSPI0_MOSI_IO0 */
5438 [ 2] = PIN_QSPI0_MISO_IO1, /* QSPI0_MISO_IO1 */
5439 [ 3] = PIN_QSPI0_IO2, /* QSPI0_IO2 */
5440 [ 4] = PIN_QSPI0_IO3, /* QSPI0_IO3 */
5441 [ 5] = PIN_QSPI0_SSL, /* QSPI0_SSL */
5442 [ 6] = PIN_QSPI1_SPCLK, /* QSPI1_SPCLK */
5443 [ 7] = PIN_QSPI1_MOSI_IO0, /* QSPI1_MOSI_IO0 */
5444 [ 8] = PIN_QSPI1_MISO_IO1, /* QSPI1_MISO_IO1 */
5445 [ 9] = PIN_QSPI1_IO2, /* QSPI1_IO2 */
5446 [10] = PIN_QSPI1_IO3, /* QSPI1_IO3 */
5447 [11] = PIN_QSPI1_SSL, /* QSPI1_SSL */
5448 [12] = PIN_RPC_INT_N, /* RPC_INT# */
5449 [13] = PIN_RPC_WP_N, /* RPC_WP# */
5450 [14] = PIN_RPC_RESET_N, /* RPC_RESET# */
5451 [15] = PIN_AVB_RX_CTL, /* AVB_RX_CTL */
5452 [16] = PIN_AVB_RXC, /* AVB_RXC */
5453 [17] = PIN_AVB_RD0, /* AVB_RD0 */
5454 [18] = PIN_AVB_RD1, /* AVB_RD1 */
5455 [19] = PIN_AVB_RD2, /* AVB_RD2 */
5456 [20] = PIN_AVB_RD3, /* AVB_RD3 */
5457 [21] = PIN_AVB_TX_CTL, /* AVB_TX_CTL */
5458 [22] = PIN_AVB_TXC, /* AVB_TXC */
5459 [23] = PIN_AVB_TD0, /* AVB_TD0 */
5460 [24] = PIN_AVB_TD1, /* AVB_TD1 */
5461 [25] = PIN_AVB_TD2, /* AVB_TD2 */
5462 [26] = PIN_AVB_TD3, /* AVB_TD3 */
5463 [27] = PIN_AVB_TXCREFCLK, /* AVB_TXCREFCLK */
5464 [28] = PIN_AVB_MDIO, /* AVB_MDIO */
5465 [29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */
5466 [30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */
5467 [31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */
5468 } },
5469 { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
5470 [ 0] = RCAR_GP_PIN(2, 12), /* AVB_LINK */
5471 [ 1] = RCAR_GP_PIN(2, 13), /* AVB_AVTP_MATCH_A */
5472 [ 2] = RCAR_GP_PIN(2, 14), /* AVB_AVTP_CAPTURE_A */
5473 [ 3] = RCAR_GP_PIN(2, 0), /* IRQ0 */
5474 [ 4] = RCAR_GP_PIN(2, 1), /* IRQ1 */
5475 [ 5] = RCAR_GP_PIN(2, 2), /* IRQ2 */
5476 [ 6] = RCAR_GP_PIN(2, 3), /* IRQ3 */
5477 [ 7] = RCAR_GP_PIN(2, 4), /* IRQ4 */
5478 [ 8] = RCAR_GP_PIN(2, 5), /* IRQ5 */
5479 [ 9] = RCAR_GP_PIN(2, 6), /* PWM0 */
5480 [10] = RCAR_GP_PIN(2, 7), /* PWM1_A */
5481 [11] = RCAR_GP_PIN(2, 8), /* PWM2_A */
5482 [12] = RCAR_GP_PIN(1, 0), /* A0 */
5483 [13] = RCAR_GP_PIN(1, 1), /* A1 */
5484 [14] = RCAR_GP_PIN(1, 2), /* A2 */
5485 [15] = RCAR_GP_PIN(1, 3), /* A3 */
5486 [16] = RCAR_GP_PIN(1, 4), /* A4 */
5487 [17] = RCAR_GP_PIN(1, 5), /* A5 */
5488 [18] = RCAR_GP_PIN(1, 6), /* A6 */
5489 [19] = RCAR_GP_PIN(1, 7), /* A7 */
5490 [20] = RCAR_GP_PIN(1, 8), /* A8 */
5491 [21] = RCAR_GP_PIN(1, 9), /* A9 */
5492 [22] = RCAR_GP_PIN(1, 10), /* A10 */
5493 [23] = RCAR_GP_PIN(1, 11), /* A11 */
5494 [24] = RCAR_GP_PIN(1, 12), /* A12 */
5495 [25] = RCAR_GP_PIN(1, 13), /* A13 */
5496 [26] = RCAR_GP_PIN(1, 14), /* A14 */
5497 [27] = RCAR_GP_PIN(1, 15), /* A15 */
5498 [28] = RCAR_GP_PIN(1, 16), /* A16 */
5499 [29] = RCAR_GP_PIN(1, 17), /* A17 */
5500 [30] = RCAR_GP_PIN(1, 18), /* A18 */
5501 [31] = RCAR_GP_PIN(1, 19), /* A19 */
5502 } },
5503 { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
5504 [ 0] = PIN_CLKOUT, /* CLKOUT */
5505 [ 1] = RCAR_GP_PIN(1, 20), /* CS0_N */
5506 [ 2] = RCAR_GP_PIN(1, 21), /* CS1_N_A26 */
5507 [ 3] = RCAR_GP_PIN(1, 22), /* BS_N */
5508 [ 4] = RCAR_GP_PIN(1, 23), /* RD_N */
5509 [ 5] = RCAR_GP_PIN(1, 24), /* RD_WR_N */
5510 [ 6] = RCAR_GP_PIN(1, 25), /* WE0_N */
5511 [ 7] = RCAR_GP_PIN(1, 26), /* WE1_N */
5512 [ 8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */
5513 [ 9] = PIN_PRESETOUT_N, /* PRESETOUT# */
5514 [10] = RCAR_GP_PIN(0, 0), /* D0 */
5515 [11] = RCAR_GP_PIN(0, 1), /* D1 */
5516 [12] = RCAR_GP_PIN(0, 2), /* D2 */
5517 [13] = RCAR_GP_PIN(0, 3), /* D3 */
5518 [14] = RCAR_GP_PIN(0, 4), /* D4 */
5519 [15] = RCAR_GP_PIN(0, 5), /* D5 */
5520 [16] = RCAR_GP_PIN(0, 6), /* D6 */
5521 [17] = RCAR_GP_PIN(0, 7), /* D7 */
5522 [18] = RCAR_GP_PIN(0, 8), /* D8 */
5523 [19] = RCAR_GP_PIN(0, 9), /* D9 */
5524 [20] = RCAR_GP_PIN(0, 10), /* D10 */
5525 [21] = RCAR_GP_PIN(0, 11), /* D11 */
5526 [22] = RCAR_GP_PIN(0, 12), /* D12 */
5527 [23] = RCAR_GP_PIN(0, 13), /* D13 */
5528 [24] = RCAR_GP_PIN(0, 14), /* D14 */
5529 [25] = RCAR_GP_PIN(0, 15), /* D15 */
5530 [26] = RCAR_GP_PIN(7, 0), /* AVS1 */
5531 [27] = RCAR_GP_PIN(7, 1), /* AVS2 */
5532 [28] = RCAR_GP_PIN(7, 2), /* GP7_02 */
5533 [29] = RCAR_GP_PIN(7, 3), /* GP7_03 */
5534 [30] = PIN_DU_DOTCLKIN0, /* DU_DOTCLKIN0 */
5535 [31] = PIN_DU_DOTCLKIN1, /* DU_DOTCLKIN1 */
5536 } },
5537 { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
5538 [ 0] = PIN_DU_DOTCLKIN2, /* DU_DOTCLKIN2 */
5539 [ 1] = PIN_DU_DOTCLKIN3, /* DU_DOTCLKIN3 */
5540 [ 2] = PIN_FSCLKST_N, /* FSCLKST# */
5541 [ 3] = PIN_EXTALR, /* EXTALR*/
5542 [ 4] = PIN_TRST_N, /* TRST# */
5543 [ 5] = PIN_TCK, /* TCK */
5544 [ 6] = PIN_TMS, /* TMS */
5545 [ 7] = PIN_TDI, /* TDI */
5546 [ 8] = SH_PFC_PIN_NONE,
5547 [ 9] = PIN_ASEBRK, /* ASEBRK */
5548 [10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */
5549 [11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */
5550 [12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */
5551 [13] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */
5552 [14] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */
5553 [15] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */
5554 [16] = RCAR_GP_PIN(3, 6), /* SD1_CLK */
5555 [17] = RCAR_GP_PIN(3, 7), /* SD1_CMD */
5556 [18] = RCAR_GP_PIN(3, 8), /* SD1_DAT0 */
5557 [19] = RCAR_GP_PIN(3, 9), /* SD1_DAT1 */
5558 [20] = RCAR_GP_PIN(3, 10), /* SD1_DAT2 */
5559 [21] = RCAR_GP_PIN(3, 11), /* SD1_DAT3 */
5560 [22] = RCAR_GP_PIN(4, 0), /* SD2_CLK */
5561 [23] = RCAR_GP_PIN(4, 1), /* SD2_CMD */
5562 [24] = RCAR_GP_PIN(4, 2), /* SD2_DAT0 */
5563 [25] = RCAR_GP_PIN(4, 3), /* SD2_DAT1 */
5564 [26] = RCAR_GP_PIN(4, 4), /* SD2_DAT2 */
5565 [27] = RCAR_GP_PIN(4, 5), /* SD2_DAT3 */
5566 [28] = RCAR_GP_PIN(4, 6), /* SD2_DS */
5567 [29] = RCAR_GP_PIN(4, 7), /* SD3_CLK */
5568 [30] = RCAR_GP_PIN(4, 8), /* SD3_CMD */
5569 [31] = RCAR_GP_PIN(4, 9), /* SD3_DAT0 */
5570 } },
5571 { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
5572 [ 0] = RCAR_GP_PIN(4, 10), /* SD3_DAT1 */
5573 [ 1] = RCAR_GP_PIN(4, 11), /* SD3_DAT2 */
5574 [ 2] = RCAR_GP_PIN(4, 12), /* SD3_DAT3 */
5575 [ 3] = RCAR_GP_PIN(4, 13), /* SD3_DAT4 */
5576 [ 4] = RCAR_GP_PIN(4, 14), /* SD3_DAT5 */
5577 [ 5] = RCAR_GP_PIN(4, 15), /* SD3_DAT6 */
5578 [ 6] = RCAR_GP_PIN(4, 16), /* SD3_DAT7 */
5579 [ 7] = RCAR_GP_PIN(4, 17), /* SD3_DS */
5580 [ 8] = RCAR_GP_PIN(3, 12), /* SD0_CD */
5581 [ 9] = RCAR_GP_PIN(3, 13), /* SD0_WP */
5582 [10] = RCAR_GP_PIN(3, 14), /* SD1_CD */
5583 [11] = RCAR_GP_PIN(3, 15), /* SD1_WP */
5584 [12] = RCAR_GP_PIN(5, 0), /* SCK0 */
5585 [13] = RCAR_GP_PIN(5, 1), /* RX0 */
5586 [14] = RCAR_GP_PIN(5, 2), /* TX0 */
5587 [15] = RCAR_GP_PIN(5, 3), /* CTS0_N */
5588 [16] = RCAR_GP_PIN(5, 4), /* RTS0_N */
5589 [17] = RCAR_GP_PIN(5, 5), /* RX1_A */
5590 [18] = RCAR_GP_PIN(5, 6), /* TX1_A */
5591 [19] = RCAR_GP_PIN(5, 7), /* CTS1_N */
5592 [20] = RCAR_GP_PIN(5, 8), /* RTS1_N */
5593 [21] = RCAR_GP_PIN(5, 9), /* SCK2 */
5594 [22] = RCAR_GP_PIN(5, 10), /* TX2_A */
5595 [23] = RCAR_GP_PIN(5, 11), /* RX2_A */
5596 [24] = RCAR_GP_PIN(5, 12), /* HSCK0 */
5597 [25] = RCAR_GP_PIN(5, 13), /* HRX0 */
5598 [26] = RCAR_GP_PIN(5, 14), /* HTX0 */
5599 [27] = RCAR_GP_PIN(5, 15), /* HCTS0_N */
5600 [28] = RCAR_GP_PIN(5, 16), /* HRTS0_N */
5601 [29] = RCAR_GP_PIN(5, 17), /* MSIOF0_SCK */
5602 [30] = RCAR_GP_PIN(5, 18), /* MSIOF0_SYNC */
5603 [31] = RCAR_GP_PIN(5, 19), /* MSIOF0_SS1 */
5604 } },
5605 { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
5606 [ 0] = RCAR_GP_PIN(5, 20), /* MSIOF0_TXD */
5607 [ 1] = RCAR_GP_PIN(5, 21), /* MSIOF0_SS2 */
5608 [ 2] = RCAR_GP_PIN(5, 22), /* MSIOF0_RXD */
5609 [ 3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */
5610 [ 4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */
5611 [ 5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */
5612 [ 6] = PIN_MLB_REF, /* MLB_REF */
5613 [ 7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */
5614 [ 8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */
5615 [ 9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */
5616 [10] = RCAR_GP_PIN(6, 3), /* SSI_SDATA1_A */
5617 [11] = RCAR_GP_PIN(6, 4), /* SSI_SDATA2_A */
5618 [12] = RCAR_GP_PIN(6, 5), /* SSI_SCK349 */
5619 [13] = RCAR_GP_PIN(6, 6), /* SSI_WS349 */
5620 [14] = RCAR_GP_PIN(6, 7), /* SSI_SDATA3 */
5621 [15] = RCAR_GP_PIN(6, 8), /* SSI_SCK4 */
5622 [16] = RCAR_GP_PIN(6, 9), /* SSI_WS4 */
5623 [17] = RCAR_GP_PIN(6, 10), /* SSI_SDATA4 */
5624 [18] = RCAR_GP_PIN(6, 11), /* SSI_SCK5 */
5625 [19] = RCAR_GP_PIN(6, 12), /* SSI_WS5 */
5626 [20] = RCAR_GP_PIN(6, 13), /* SSI_SDATA5 */
5627 [21] = RCAR_GP_PIN(6, 14), /* SSI_SCK6 */
5628 [22] = RCAR_GP_PIN(6, 15), /* SSI_WS6 */
5629 [23] = RCAR_GP_PIN(6, 16), /* SSI_SDATA6 */
5630 [24] = RCAR_GP_PIN(6, 17), /* SSI_SCK78 */
5631 [25] = RCAR_GP_PIN(6, 18), /* SSI_WS78 */
5632 [26] = RCAR_GP_PIN(6, 19), /* SSI_SDATA7 */
5633 [27] = RCAR_GP_PIN(6, 20), /* SSI_SDATA8 */
5634 [28] = RCAR_GP_PIN(6, 21), /* SSI_SDATA9_A */
5635 [29] = RCAR_GP_PIN(6, 22), /* AUDIO_CLKA_A */
5636 [30] = RCAR_GP_PIN(6, 23), /* AUDIO_CLKB_B */
5637 [31] = RCAR_GP_PIN(6, 24), /* USB0_PWEN */
5638 } },
5639 { PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) {
5640 [ 0] = RCAR_GP_PIN(6, 25), /* USB0_OVC */
5641 [ 1] = RCAR_GP_PIN(6, 26), /* USB1_PWEN */
5642 [ 2] = RCAR_GP_PIN(6, 27), /* USB1_OVC */
5643 [ 3] = RCAR_GP_PIN(6, 28), /* USB30_PWEN */
5644 [ 4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */
5645 [ 5] = RCAR_GP_PIN(6, 30), /* USB31_PWEN */
5646 [ 6] = RCAR_GP_PIN(6, 31), /* USB31_OVC */
5647 [ 7] = SH_PFC_PIN_NONE,
5648 [ 8] = SH_PFC_PIN_NONE,
5649 [ 9] = SH_PFC_PIN_NONE,
5650 [10] = SH_PFC_PIN_NONE,
5651 [11] = SH_PFC_PIN_NONE,
5652 [12] = SH_PFC_PIN_NONE,
5653 [13] = SH_PFC_PIN_NONE,
5654 [14] = SH_PFC_PIN_NONE,
5655 [15] = SH_PFC_PIN_NONE,
5656 [16] = SH_PFC_PIN_NONE,
5657 [17] = SH_PFC_PIN_NONE,
5658 [18] = SH_PFC_PIN_NONE,
5659 [19] = SH_PFC_PIN_NONE,
5660 [20] = SH_PFC_PIN_NONE,
5661 [21] = SH_PFC_PIN_NONE,
5662 [22] = SH_PFC_PIN_NONE,
5663 [23] = SH_PFC_PIN_NONE,
5664 [24] = SH_PFC_PIN_NONE,
5665 [25] = SH_PFC_PIN_NONE,
5666 [26] = SH_PFC_PIN_NONE,
5667 [27] = SH_PFC_PIN_NONE,
5668 [28] = SH_PFC_PIN_NONE,
5669 [29] = SH_PFC_PIN_NONE,
5670 [30] = SH_PFC_PIN_NONE,
5671 [31] = SH_PFC_PIN_NONE,
5672 } },
5673 { /* sentinel */ },
5674 };
5675
5676 static const struct sh_pfc_soc_operations r8a77950_pfc_ops = {
5677 .pin_to_pocctrl = r8a77950_pin_to_pocctrl,
5678 .get_bias = rcar_pinmux_get_bias,
5679 .set_bias = rcar_pinmux_set_bias,
5680 };
5681
5682 const struct sh_pfc_soc_info r8a77950_pinmux_info = {
5683 .name = "r8a77950_pfc",
5684 .ops = &r8a77950_pfc_ops,
5685 .unlock_reg = 0xe6060000, /* PMMR */
5686
5687 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
5688
5689 .pins = pinmux_pins,
5690 .nr_pins = ARRAY_SIZE(pinmux_pins),
5691 .groups = pinmux_groups,
5692 .nr_groups = ARRAY_SIZE(pinmux_groups),
5693 .functions = pinmux_functions,
5694 .nr_functions = ARRAY_SIZE(pinmux_functions),
5695
5696 .cfg_regs = pinmux_config_regs,
5697 .drive_regs = pinmux_drive_regs,
5698 .bias_regs = pinmux_bias_regs,
5699 .ioctrl_regs = pinmux_ioctrl_regs,
5700
5701 .pinmux_data = pinmux_data,
5702 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
5703 };
5704