Searched refs:ulClock (Results 1 – 10 of 10) sorted by relevance
224 engine_clock_parameters.sReserved.ulClock = in atomctrl_set_engine_dram_timings_rv770()295 mpll_parameters.ulClock = cpu_to_le32(clock_value); in atomctrl_get_memory_pll_dividers_si()344 mpll_parameters.ulClock.ulClock = cpu_to_le32(clock_value); in atomctrl_get_memory_pll_dividers_vi()352 (uint32_t)mpll_parameters.ulClock.ucPostDiv; in atomctrl_get_memory_pll_dividers_vi()365 mpll_parameters.ulClock.ulClock = cpu_to_le32(clock_value); in atomctrl_get_memory_pll_dividers_ai()379 mpll_param->ulClock = in atomctrl_get_memory_pll_dividers_ai()380 le32_to_cpu(mpll_parameters.ulClock.ulClock); in atomctrl_get_memory_pll_dividers_ai()381 mpll_param->ulPostDiv = mpll_parameters.ulClock.ucPostDiv; in atomctrl_get_memory_pll_dividers_ai()395 pll_parameters.ulClock = cpu_to_le32(clock_value); in atomctrl_get_engine_pll_dividers_kong()403 dividers->real_clock = le32_to_cpu(pll_parameters.ulClock); in atomctrl_get_engine_pll_dividers_kong()[all …]
61 uint32_t ulClock; /* the actual clock */ member
141 uint32_t ulClock; member
266 dividers->ulClock = le32_to_cpu(pll_output->gpuclock_10khz); in pp_atomfwctrl_get_gpu_pll_dividers_vega10()
1057 args.v4.ulClock = cpu_to_le32(clock); /* 10 khz */ in amdgpu_atombios_get_clock_dividers()1062 dividers->real_clock = le32_to_cpu(args.v4.ulClock); in amdgpu_atombios_get_clock_dividers()1067 args.v6_in.ulClock.ulComputeClockFlag = clock_type; in amdgpu_atombios_get_clock_dividers()1068 args.v6_in.ulClock.ulClockFreq = cpu_to_le32(clock); /* 10 khz */ in amdgpu_atombios_get_clock_dividers()1077 dividers->real_clock = le32_to_cpu(args.v6_out.ulClock.ulClock); in amdgpu_atombios_get_clock_dividers()1078 dividers->post_divider = args.v6_out.ulClock.ucPostDiv; in amdgpu_atombios_get_clock_dividers()1107 args.ulClock = cpu_to_le32(clock); /* 10 khz */ in amdgpu_atombios_get_memory_pll_dividers()1152 args.sReserved.ulClock = cpu_to_le32(mem_clock & SET_CLOCK_FREQ_MASK); in amdgpu_atombios_set_engine_dram_timings()
440 …ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Di… member449 ULONG ulClock; //When return, [23:0] return real clock member496 ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter member518 ULONG ulClock:24; //Input= target clock, output = actual clock member520 ULONG ulClock:24; //Input= target clock, output = actual clock529 ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter member546 ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter member558 …COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 ulClock; //Output Parameter: ucPostDiv=DFS divider member571 ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter member582 …COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 ulClock; //Output Parameter: ucPostDiv=DFS divider member[all …]
2849 args.v1.ulClock = cpu_to_le32(clock); /* 10 khz */ in radeon_atom_get_clock_dividers()2863 args.v2.ulClock = cpu_to_le32(clock); /* 10 khz */ in radeon_atom_get_clock_dividers()2871 dividers->enable_post_div = (le32_to_cpu(args.v2.ulClock) & (1 << 24)) ? in radeon_atom_get_clock_dividers()2873 dividers->vco_mode = (le32_to_cpu(args.v2.ulClock) & (1 << 25)) ? 1 : 0; in radeon_atom_get_clock_dividers()2917 args.v4.ulClock = cpu_to_le32(clock); /* 10 khz */ in radeon_atom_get_clock_dividers()2922 dividers->real_clock = le32_to_cpu(args.v4.ulClock); in radeon_atom_get_clock_dividers()2927 args.v6_in.ulClock.ulComputeClockFlag = clock_type; in radeon_atom_get_clock_dividers()2928 args.v6_in.ulClock.ulClockFreq = cpu_to_le32(clock); /* 10 khz */ in radeon_atom_get_clock_dividers()2937 dividers->real_clock = le32_to_cpu(args.v6_out.ulClock.ulClock); in radeon_atom_get_clock_dividers()2938 dividers->post_divider = args.v6_out.ulClock.ucPostDiv; in radeon_atom_get_clock_dividers()[all …]
410 …ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Di… member419 ULONG ulClock; //When return, [23:0] return real clock member462 ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter member484 ULONG ulClock:24; //Input= target clock, output = actual clock member486 ULONG ulClock:24; //Input= target clock, output = actual clock 495 ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter member512 ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter member523 …COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 ulClock; //Output Parameter: ucPostDiv=DFS divider member543 ULONG ulClock; member568 ATOM_COMPUTE_CLOCK_FREQ ulClock; member[all …]
2441 u32 ulClock = state->config.clock; in CDRXD() local2545 state->osc_clock_freq = (u16) ulClock; in CDRXD()
974 mem_level->MclkFrequency = (uint32_t)mpll_param.ulClock; in vegam_calculate_mclk_params()