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Searched refs:uhs (Results 1 – 25 of 138) sorted by relevance

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/linux-6.1.9/arch/riscv/boot/dts/microchip/
Dmpfs-polarberry.dts75 sd-uhs-sdr12;
76 sd-uhs-sdr25;
77 sd-uhs-sdr50;
78 sd-uhs-sdr104;
Dmpfs-sev-kit.dts108 sd-uhs-sdr12;
109 sd-uhs-sdr25;
110 sd-uhs-sdr50;
111 sd-uhs-sdr104;
Dmpfs-icicle-kit.dts117 sd-uhs-sdr12;
118 sd-uhs-sdr25;
119 sd-uhs-sdr50;
120 sd-uhs-sdr104;
Dmpfs-m100pfsevp.dts124 sd-uhs-sdr12;
125 sd-uhs-sdr25;
126 sd-uhs-sdr50;
127 sd-uhs-sdr104;
/linux-6.1.9/arch/arm64/boot/dts/freescale/
Dfsl-ls1012a-rdb.dts29 sd-uhs-sdr104;
30 sd-uhs-sdr50;
31 sd-uhs-sdr25;
32 sd-uhs-sdr12;
Dfsl-lx2160a-clearfog-itx.dtsi92 sd-uhs-sdr104;
93 sd-uhs-sdr50;
94 sd-uhs-sdr25;
95 sd-uhs-sdr12;
Dfsl-ls1046a-rdb.dts41 sd-uhs-sdr104;
42 sd-uhs-sdr50;
43 sd-uhs-sdr25;
44 sd-uhs-sdr12;
Dfsl-lx2160a-rdb.dts130 sd-uhs-sdr104;
131 sd-uhs-sdr50;
132 sd-uhs-sdr25;
133 sd-uhs-sdr12;
Dfsl-ls1028a-kontron-sl28.dts99 sd-uhs-sdr104;
100 sd-uhs-sdr50;
101 sd-uhs-sdr25;
102 sd-uhs-sdr12;
Dfsl-ls1028a-rdb.dts162 sd-uhs-sdr104;
163 sd-uhs-sdr50;
164 sd-uhs-sdr25;
165 sd-uhs-sdr12;
Dfsl-lx2162a-qds.dts237 sd-uhs-sdr104;
238 sd-uhs-sdr50;
239 sd-uhs-sdr25;
240 sd-uhs-sdr12;
/linux-6.1.9/arch/arm/boot/dts/
Drk3288-veyron-sdmmc.dtsi83 sd-uhs-sdr12;
84 sd-uhs-sdr25;
85 sd-uhs-sdr50;
86 sd-uhs-sdr104;
Dstih410-b2120.dts39 sd-uhs-sdr50;
40 sd-uhs-sdr104;
41 sd-uhs-ddr50;
Dstih418-b2199.dts92 sd-uhs-sdr50;
93 sd-uhs-sdr104;
94 sd-uhs-ddr50;
Drk3288-phycore-rdk.dts231 sd-uhs-sdr12;
232 sd-uhs-sdr25;
233 sd-uhs-sdr50;
234 sd-uhs-sdr104;
/linux-6.1.9/Documentation/devicetree/bindings/mmc/
Dsocionext,uniphier-sd.yaml94 pinctrl-names = "default", "uhs";
104 sd-uhs-sdr12;
105 sd-uhs-sdr25;
106 sd-uhs-sdr50;
Dsdhci-st.txt51 - sd-uhs-sdr50: To enable the SDR50 in the mmcss.
54 - sd-uhs-sdr104: To enable the SDR104 in the mmcss.
57 - sd-uhs-ddr50: To enable the DDR50 in the mmcss.
107 sd-uhs-sdr50;
108 sd-uhs-sdr104;
109 sd-uhs-ddr50;
Dsdhci-sprd.txt24 - pinctrl-1: should contain uhs mode pin control
35 - sprd,phy-delay-sd-uhs-sdr50: Delay value for SD UHS SDR50 timing.
36 - sprd,phy-delay-sd-uhs-sdr104: Delay value for SD UHS SDR50 timing.
60 sprd,phy-delay-sd-uhs-sdr104 = <0x3f 0x7f 0x2e 0x2e>;
Dbrcm,sdhci-brcmstb.yaml93 sd-uhs-sdr50;
94 sd-uhs-ddr50;
95 sd-uhs-sdr104;
Dcdns,sdhci.yaml49 cdns,phy-input-delay-sd-uhs-sdr12:
55 cdns,phy-input-delay-sd-uhs-sdr25:
61 cdns,phy-input-delay-sd-uhs-sdr50:
67 cdns,phy-input-delay-sd-uhs-ddr50:
/linux-6.1.9/drivers/mmc/host/
Dsdhci-pxav3.c240 static void pxav3_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs) in pxav3_set_uhs_signaling() argument
254 switch (uhs) { in pxav3_set_uhs_signaling()
280 if (uhs == MMC_TIMING_UHS_SDR50 || in pxav3_set_uhs_signaling()
281 uhs == MMC_TIMING_UHS_DDR50) { in pxav3_set_uhs_signaling()
284 } else if (uhs == MMC_TIMING_MMC_HS) { in pxav3_set_uhs_signaling()
297 __func__, uhs, ctrl_2); in pxav3_set_uhs_signaling()
/linux-6.1.9/arch/arm64/boot/dts/amlogic/
Dmeson-gxl-s905x-libretech-cc-v2.dts248 sd-uhs-sdr12;
249 sd-uhs-sdr25;
250 sd-uhs-sdr50;
251 sd-uhs-ddr50;
Dmeson-gxbb-p20x.dtsi196 sd-uhs-sdr12;
197 sd-uhs-sdr25;
198 sd-uhs-sdr50;
/linux-6.1.9/arch/arm64/boot/dts/rockchip/
Drk3308-roc-cc.dts181 sd-uhs-sdr25;
182 sd-uhs-sdr50;
183 sd-uhs-sdr104;
/linux-6.1.9/arch/arm64/boot/dts/mediatek/
Dmt8183-pumpkin.dts167 sd-uhs-sdr50;
168 sd-uhs-sdr104;
279 mmc0_pins_uhs: mmc0-pins-uhs {
337 mmc1_pins_uhs: mmc1-pins-uhs {

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