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Searched refs:ucode (Results 1 – 25 of 84) sorted by relevance

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/linux-6.1.9/drivers/net/wireless/broadcom/brcm80211/brcmsmac/
Ducode_loader.c40 int brcms_ucode_data_init(struct brcms_info *wl, struct brcms_ucode *ucode) in brcms_ucode_data_init() argument
47 brcms_ucode_init_buf(wl, (void **)&ucode->d11lcn0bsinitvals24, in brcms_ucode_data_init()
50 rc : brcms_ucode_init_buf(wl, (void **)&ucode->d11lcn0initvals24, in brcms_ucode_data_init()
53 rc : brcms_ucode_init_buf(wl, (void **)&ucode->d11lcn1bsinitvals24, in brcms_ucode_data_init()
56 rc : brcms_ucode_init_buf(wl, (void **)&ucode->d11lcn1initvals24, in brcms_ucode_data_init()
59 brcms_ucode_init_buf(wl, (void **)&ucode->d11lcn2bsinitvals24, in brcms_ucode_data_init()
62 rc : brcms_ucode_init_buf(wl, (void **)&ucode->d11lcn2initvals24, in brcms_ucode_data_init()
65 rc : brcms_ucode_init_buf(wl, (void **)&ucode->d11n0absinitvals16, in brcms_ucode_data_init()
68 rc : brcms_ucode_init_buf(wl, (void **)&ucode->d11n0bsinitvals16, in brcms_ucode_data_init()
71 rc : brcms_ucode_init_buf(wl, (void **)&ucode->d11n0initvals16, in brcms_ucode_data_init()
[all …]
Ducode_loader.h46 int brcms_ucode_data_init(struct brcms_info *wl, struct brcms_ucode *ucode);
48 void brcms_ucode_data_free(struct brcms_ucode *ucode);
/linux-6.1.9/drivers/gpu/drm/amd/amdgpu/
Damdgpu_ucode.c743 struct amdgpu_firmware_info *ucode, in amdgpu_ucode_init_single_fw() argument
756 if (NULL == ucode->fw) in amdgpu_ucode_init_single_fw()
759 ucode->mc_addr = mc_addr; in amdgpu_ucode_init_single_fw()
760 ucode->kaddr = kptr; in amdgpu_ucode_init_single_fw()
762 if (ucode->ucode_id == AMDGPU_UCODE_ID_STORAGE) in amdgpu_ucode_init_single_fw()
765 header = (const struct common_firmware_header *)ucode->fw->data; in amdgpu_ucode_init_single_fw()
766 cp_hdr = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data; in amdgpu_ucode_init_single_fw()
767 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *)ucode->fw->data; in amdgpu_ucode_init_single_fw()
768 dmcu_hdr = (const struct dmcu_firmware_header_v1_0 *)ucode->fw->data; in amdgpu_ucode_init_single_fw()
769 dmcub_hdr = (const struct dmcub_firmware_header_v1_0 *)ucode->fw->data; in amdgpu_ucode_init_single_fw()
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Damdgpu_cgs.c213 struct amdgpu_firmware_info *ucode; in amdgpu_cgs_get_firmware_info() local
216 ucode = &adev->firmware.ucode[id]; in amdgpu_cgs_get_firmware_info()
217 if (ucode->fw == NULL) in amdgpu_cgs_get_firmware_info()
220 gpu_addr = ucode->mc_addr; in amdgpu_cgs_get_firmware_info()
221 header = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data; in amdgpu_cgs_get_firmware_info()
230 info->kptr = ucode->kaddr; in amdgpu_cgs_get_firmware_info()
248 struct amdgpu_firmware_info *ucode = NULL; in amdgpu_cgs_get_firmware_info() local
429 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC]; in amdgpu_cgs_get_firmware_info()
430 ucode->ucode_id = AMDGPU_UCODE_ID_SMC; in amdgpu_cgs_get_firmware_info()
431 ucode->fw = adev->pm.fw; in amdgpu_cgs_get_firmware_info()
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Damdgpu_rlc.c327 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G]; in amdgpu_gfx_rlc_init_microcode_v2_0()
363 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL]; in amdgpu_gfx_rlc_init_microcode_v2_1()
371 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM]; in amdgpu_gfx_rlc_init_microcode_v2_1()
379 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM]; in amdgpu_gfx_rlc_init_microcode_v2_1()
401 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_IRAM]; in amdgpu_gfx_rlc_init_microcode_v2_2()
409 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_DRAM]; in amdgpu_gfx_rlc_init_microcode_v2_2()
436 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_P]; in amdgpu_gfx_rlc_init_microcode_v2_3()
444 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_V]; in amdgpu_gfx_rlc_init_microcode_v2_3()
472 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS]; in amdgpu_gfx_rlc_init_microcode_v2_4()
480 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SE0_TAP_DELAYS]; in amdgpu_gfx_rlc_init_microcode_v2_4()
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Damdgpu_psp.c597 struct amdgpu_firmware_info *ucode, in psp_cmd_submit_buf() argument
653 if (ucode) in psp_cmd_submit_buf()
655 amdgpu_ucode_name(ucode->ucode_id), ucode->ucode_id); in psp_cmd_submit_buf()
663 if ((ucode && amdgpu_sriov_vf(psp->adev)) || !timeout) { in psp_cmd_submit_buf()
669 if (ucode) { in psp_cmd_submit_buf()
670 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo; in psp_cmd_submit_buf()
671 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi; in psp_cmd_submit_buf()
2123 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode, in psp_get_fw_type() argument
2126 switch (ucode->ucode_id) { in psp_get_fw_type()
2316 struct amdgpu_firmware_info *ucode) in psp_print_fw_hdr() argument
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Daldebaran.c213 struct amdgpu_firmware_info *ucode; in aldebaran_mode2_restore_ip() local
220 ucode = &adev->firmware.ucode[i]; in aldebaran_mode2_restore_ip()
221 if (!ucode->fw) in aldebaran_mode2_restore_ip()
223 switch (ucode->ucode_id) { in aldebaran_mode2_restore_ip()
238 ucode_list[ucode_count++] = ucode; in aldebaran_mode2_restore_ip()
/linux-6.1.9/drivers/crypto/marvell/octeontx/
Dotx_cptpf_ucode.c97 static void set_ucode_filename(struct otx_cpt_ucode *ucode, in set_ucode_filename() argument
100 strscpy(ucode->filename, filename, OTX_CPT_UCODE_NAME_LENGTH); in set_ucode_filename()
188 eng_grp->g->grp[eng_grp->mirror.idx].ucode[0].align_dma; in cpt_set_ucode_base()
190 dma_addr = eng_grp->ucode[0].align_dma; in cpt_set_ucode_base()
325 set_ucode_filename(&tar_info->ucode, filename); in process_tar_file()
326 memcpy(tar_info->ucode.ver_str, ucode_hdr->ver_str, in process_tar_file()
328 tar_info->ucode.ver_num = ucode_hdr->ver_num; in process_tar_file()
329 tar_info->ucode.type = ucode_type; in process_tar_file()
330 tar_info->ucode.size = ucode_size; in process_tar_file()
360 if (!is_eng_type(curr->ucode.type, ucode_type)) in get_uc_from_tar_archive()
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Dotx_cptpf_mbox.c140 struct otx_cpt_ucode *ucode; in otx_cpt_bind_vq_to_grp() local
165 ucode = &eng_grp->g->grp[eng_grp->mirror.idx].ucode[0]; in otx_cpt_bind_vq_to_grp()
167 ucode = &eng_grp->ucode[0]; in otx_cpt_bind_vq_to_grp()
169 if (otx_cpt_uc_supports_eng_type(ucode, OTX_CPT_SE_TYPES)) in otx_cpt_bind_vq_to_grp()
171 else if (otx_cpt_uc_supports_eng_type(ucode, OTX_CPT_AE_TYPES)) in otx_cpt_bind_vq_to_grp()
Dotx_cptpf_ucode.h97 struct otx_cpt_ucode ucode;/* microcode information */ member
115 struct otx_cpt_ucode *ucode; /* ucode used by these engines */ member
141 struct otx_cpt_ucode ucode[OTX_CPT_MAX_ETYPES_PER_GRP]; member
176 int otx_cpt_uc_supports_eng_type(struct otx_cpt_ucode *ucode, int eng_type);
/linux-6.1.9/drivers/crypto/marvell/octeontx2/
Dotx2_cptpf_ucode.c62 if (eng_grp->ucode[1].type) in is_2nd_ucode_used()
68 static void set_ucode_filename(struct otx2_cpt_ucode *ucode, in set_ucode_filename() argument
71 strscpy(ucode->filename, filename, OTX2_CPT_NAME_LENGTH); in set_ucode_filename()
185 dma_addr = engs->ucode->dma; in cptx_set_ucode_base()
389 set_ucode_filename(&uc_info->ucode, filename); in load_fw()
390 memcpy(uc_info->ucode.ver_str, ucode_hdr->ver_str, in load_fw()
392 uc_info->ucode.ver_num = ucode_hdr->ver_num; in load_fw()
393 uc_info->ucode.type = ucode_type; in load_fw()
394 uc_info->ucode.size = ucode_size; in load_fw()
426 if (!is_eng_type(curr->ucode.type, ucode_type)) in get_ucode()
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Dotx2_cptpf_ucode.h90 struct otx2_cpt_ucode ucode;/* microcode information */ member
110 struct otx2_cpt_ucode *ucode; /* ucode used by these engines */ member
135 struct otx2_cpt_ucode ucode[OTX2_CPT_MAX_ETYPES_PER_GRP]; member
/linux-6.1.9/drivers/soc/fsl/qe/
Dqe.c405 const struct qe_microcode *ucode) in qe_upload_microcode() argument
407 const __be32 *code = base + be32_to_cpu(ucode->code_offset); in qe_upload_microcode()
410 if (ucode->major || ucode->minor || ucode->revision) in qe_upload_microcode()
413 ucode->id, ucode->major, ucode->minor, ucode->revision); in qe_upload_microcode()
416 "uploading microcode '%s'\n", ucode->id); in qe_upload_microcode()
419 iowrite32be(be32_to_cpu(ucode->iram_offset) | QE_IRAM_IADD_AIE | QE_IRAM_IADD_BADDR, in qe_upload_microcode()
422 for (i = 0; i < be32_to_cpu(ucode->count); i++) in qe_upload_microcode()
534 const struct qe_microcode *ucode = &firmware->microcode[i]; in qe_upload_firmware() local
537 if (ucode->code_offset) in qe_upload_firmware()
538 qe_upload_microcode(firmware, ucode); in qe_upload_firmware()
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/linux-6.1.9/drivers/crypto/cavium/nitrox/
Dnitrox_main.c60 struct ucode { struct
114 struct ucode *ucode; in nitrox_load_fw() local
132 ucode = (struct ucode *)fw->data; in nitrox_load_fw()
134 ucode_size = be32_to_cpu(ucode->code_size) * 2; in nitrox_load_fw()
141 ucode_data = ucode->code; in nitrox_load_fw()
144 memcpy(&ndev->hw.fw_name[0][0], ucode->version, (VERSION_LEN - 2)); in nitrox_load_fw()
183 ucode = (struct ucode *)fw->data; in nitrox_load_fw()
185 ucode_size = be32_to_cpu(ucode->code_size) * 2; in nitrox_load_fw()
192 ucode_data = ucode->code; in nitrox_load_fw()
195 memcpy(&ndev->hw.fw_name[1][0], ucode->version, (VERSION_LEN - 2)); in nitrox_load_fw()
/linux-6.1.9/drivers/input/touchscreen/
Dhideep.c412 const __be32 *ucode, size_t xfer_count) in hideep_program_page() argument
438 val = be32_to_cpu(ucode[0]); in hideep_program_page()
442 ucode, xfer_count); in hideep_program_page()
444 val = be32_to_cpu(ucode[xfer_count - 1]); in hideep_program_page()
461 const __be32 *ucode, size_t ucode_len) in hideep_program_nvm() argument
476 xfer_count = xfer_len / sizeof(*ucode); in hideep_program_nvm()
488 if (memcmp(ucode, current_ucode, xfer_len)) { in hideep_program_nvm()
490 ucode, xfer_count); in hideep_program_nvm()
501 ucode += xfer_count; in hideep_program_nvm()
510 const __be32 *ucode, size_t ucode_len) in hideep_verify_nvm() argument
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/linux-6.1.9/Documentation/x86/
Dmicrocode.rst72 if [ -d /lib/firmware/amd-ucode ]; then
73 cat /lib/firmware/amd-ucode/microcode_amd*.bin > $DSTDIR/AuthenticAMD.bin
76 if [ -d /lib/firmware/intel-ucode ]; then
77 cat /lib/firmware/intel-ucode/* > $DSTDIR/GenuineIntel.bin
80 find . | cpio -o -H newc >../ucode.cpio
83 cat ucode.cpio $INITRD.orig > $INITRD
104 /lib/firmware/{intel-ucode,amd-ucode}. The default distro installation
220 CONFIG_EXTRA_FIRMWARE="intel-ucode/06-3a-09 amd-ucode/microcode_amd_fam15h.bin"
226 |-- amd-ucode
230 |-- intel-ucode
Dtsx_async_abort.rst46 ucode needed Mitigation is enabled. CPU is affected and MD_CLEAR is not
71 …0 1 0 HW default No Need ucode update Need ucode up…
86 …0 1 0 HW default No Need ucode update Need ucode up…
101 …0 1 0 HW default No Need ucode update Need ucode up…
/linux-6.1.9/drivers/net/wireless/intel/iwlwifi/
Diwl-drv.c437 const struct iwl_ucode_header *ucode = (const void *)ucode_raw->data; in iwl_parse_v1_v2_firmware() local
442 drv->fw.ucode_ver = le32_to_cpu(ucode->ver); in iwl_parse_v1_v2_firmware()
452 build = le32_to_cpu(ucode->u.v2.build); in iwl_parse_v1_v2_firmware()
454 le32_to_cpu(ucode->u.v2.inst_size)); in iwl_parse_v1_v2_firmware()
456 le32_to_cpu(ucode->u.v2.data_size)); in iwl_parse_v1_v2_firmware()
458 le32_to_cpu(ucode->u.v2.init_size)); in iwl_parse_v1_v2_firmware()
460 le32_to_cpu(ucode->u.v2.init_data_size)); in iwl_parse_v1_v2_firmware()
461 src = ucode->u.v2.data; in iwl_parse_v1_v2_firmware()
473 le32_to_cpu(ucode->u.v1.inst_size)); in iwl_parse_v1_v2_firmware()
475 le32_to_cpu(ucode->u.v1.data_size)); in iwl_parse_v1_v2_firmware()
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/linux-6.1.9/arch/x86/kernel/cpu/microcode/
Damd.c295 static size_t parse_container(u8 *ucode, size_t size, struct cont_desc *desc) in parse_container() argument
299 u32 *hdr = (u32 *)ucode; in parse_container()
303 if (!verify_equivalence_table(ucode, size, true)) in parse_container()
306 buf = ucode; in parse_container()
361 desc->data = ucode; in parse_container()
375 static void scan_containers(u8 *ucode, size_t size, struct cont_desc *desc) in scan_containers() argument
378 size_t s = parse_container(ucode, size, desc); in scan_containers()
384 ucode += s; in scan_containers()
418 apply_microcode_early_amd(u32 cpuid_1_eax, void *ucode, size_t size, bool save_patch) in apply_microcode_early_amd() argument
436 scan_containers(ucode, size, &desc); in apply_microcode_early_amd()
/linux-6.1.9/drivers/gpu/drm/nouveau/nvkm/engine/gr/
Dctxnv40.h13 u32 *ucode; member
27 u32 *ctxprog = ctx->ucode; in cp_out()
61 u32 *ctxprog = ctx->ucode; in cp_name()
Dgf104.c133 .fecs.ucode = &gf100_gr_fecs_ucode,
134 .gpccs.ucode = &gf100_gr_gpccs_ucode,
Dgf110.c105 .fecs.ucode = &gf100_gr_fecs_ucode,
106 .gpccs.ucode = &gf100_gr_gpccs_ucode,
Dgk110b.c124 .fecs.ucode = &gk110_gr_fecs_ucode,
125 .gpccs.ucode = &gk110_gr_gpccs_ucode,
Dgf108.c131 .fecs.ucode = &gf100_gr_fecs_ucode,
132 .gpccs.ucode = &gf100_gr_gpccs_ucode,
Dgf119.c196 .fecs.ucode = &gf100_gr_fecs_ucode,
197 .gpccs.ucode = &gf100_gr_gpccs_ucode,

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