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Searched refs:uart0_parents (Results 1 – 5 of 5) sorted by relevance

/linux-6.1.9/drivers/clk/spear/
Dspear3xx_clock.c128 static const char *uart0_parents[] = { "pll3_clk", "uart_syn_gclk", }; variable
440 clk = clk_register_mux(NULL, "uart0_mclk", uart0_parents, in spear3xx_clk_init()
441 ARRAY_SIZE(uart0_parents), in spear3xx_clk_init()
Dspear1340_clock.c419 static const char *uart0_parents[] = { "pll5_clk", "osc_24m_clk", variable
636 clk = clk_register_mux(NULL, "uart0_mclk", uart0_parents, in spear1340_clk_init()
637 ARRAY_SIZE(uart0_parents), in spear1340_clk_init()
Dspear1310_clock.c358 static const char *uart0_parents[] = { "pll5_clk", "uart_syn_gclk", }; variable
557 clk = clk_register_mux(NULL, "uart0_mclk", uart0_parents, in spear1310_clk_init()
558 ARRAY_SIZE(uart0_parents), in spear1310_clk_init()
/linux-6.1.9/drivers/clk/mediatek/
Dclk-mt8516.c74 static const char * const uart0_parents[] __initconst = { variable
364 MUX(CLK_TOP_UART0_SEL, "uart0_sel", uart0_parents,
Dclk-mt8167.c88 static const char * const uart0_parents[] __initconst = { variable
524 MUX(CLK_TOP_UART0_SEL, "uart0_sel", uart0_parents,