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Searched refs:train_set (Results 1 – 10 of 10) sorted by relevance

/linux-6.1.9/drivers/gpu/drm/i915/display/
Dintel_dp_link_training.c435 intel_dp->train_set[lane] = in intel_dp_get_adjust_train()
455 u8 buf[sizeof(intel_dp->train_set) + 1]; in intel_dp_set_link_train()
463 memcpy(buf + 1, intel_dp->train_set, crtc_state->lane_count); in intel_dp_set_link_train()
505 #define _TRAIN_SET_VSWING_ARGS(train_set) \ argument
506 ((train_set) & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT, \
507 (train_set) & DP_TRAIN_MAX_SWING_REACHED ? "(max)" : ""
508 #define TRAIN_SET_VSWING_ARGS(train_set) \ argument
509 _TRAIN_SET_VSWING_ARGS((train_set)[0]), \
510 _TRAIN_SET_VSWING_ARGS((train_set)[1]), \
511 _TRAIN_SET_VSWING_ARGS((train_set)[2]), \
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Dg4x_dp.c790 u8 train_set = intel_dp->train_set[0]; in vlv_set_signal_levels() local
792 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { in vlv_set_signal_levels()
795 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { in vlv_set_signal_levels()
818 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { in vlv_set_signal_levels()
837 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { in vlv_set_signal_levels()
852 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { in vlv_set_signal_levels()
876 u8 train_set = intel_dp->train_set[0]; in chv_set_signal_levels() local
878 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { in chv_set_signal_levels()
880 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { in chv_set_signal_levels()
903 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { in chv_set_signal_levels()
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Dintel_ddi.c1337 u8 train_set = intel_dp->train_set[lane]; in intel_ddi_dp_level() local
1340 return train_set & DP_TX_FFE_PRESET_VALUE_MASK; in intel_ddi_dp_level()
1342 u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | in intel_ddi_dp_level()
Dintel_display_types.h1660 u8 train_set[4]; member
Dintel_dp.c2120 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set)); in intel_dp_set_link_params()
3701 intel_dp->train_set, crtc_state->lane_count); in intel_dp_process_phy_request()
Dintel_display_debugfs.c1293 intel_dp->train_set[0]); in i915_displayport_test_data_show()
/linux-6.1.9/drivers/gpu/drm/amd/amdgpu/
Datombios_dp.c205 u8 train_set[4]) in amdgpu_atombios_dp_get_adjust_train()
237 train_set[lane] = v | p; in amdgpu_atombios_dp_get_adjust_train()
496 u8 train_set[4]; member
508 0, dp_info->train_set[0]); /* sets all lanes at once */ in amdgpu_atombios_dp_update_vs_emph()
512 dp_info->train_set, dp_info->dp_lane_count); in amdgpu_atombios_dp_update_vs_emph()
606 memset(dp_info->train_set, 0, 4); in amdgpu_atombios_dp_link_train_cr()
630 if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) in amdgpu_atombios_dp_link_train_cr()
638 if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { in amdgpu_atombios_dp_link_train_cr()
647 voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; in amdgpu_atombios_dp_link_train_cr()
651 dp_info->train_set); in amdgpu_atombios_dp_link_train_cr()
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/linux-6.1.9/drivers/gpu/drm/radeon/
Datombios_dp.c259 u8 train_set[4]) in dp_get_adjust_train()
291 train_set[lane] = v | p; in dp_get_adjust_train()
546 u8 train_set[4]; member
558 0, dp_info->train_set[0]); /* sets all lanes at once */ in radeon_dp_update_vs_emph()
562 dp_info->train_set, dp_info->dp_lane_count); in radeon_dp_update_vs_emph()
673 memset(dp_info->train_set, 0, 4); in radeon_dp_link_train_cr()
697 if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) in radeon_dp_link_train_cr()
705 if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { in radeon_dp_link_train_cr()
714 voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; in radeon_dp_link_train_cr()
717 dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set); in radeon_dp_link_train_cr()
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/linux-6.1.9/drivers/gpu/drm/xlnx/
Dzynqmp_dp.c321 u8 train_set[ZYNQMP_DP_MAX_LANES]; member
615 u8 *train_set = dp->train_set; in zynqmp_dp_adjust_train() local
637 train_set[i] = voltage | preemphasis; in zynqmp_dp_adjust_train()
655 ret = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, dp->train_set, in zynqmp_dp_update_vs_emph()
663 u8 train = dp->train_set[i]; in zynqmp_dp_update_vs_emph()
721 if (!(dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED)) in zynqmp_dp_link_train_cr()
726 if ((dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == vs) in zynqmp_dp_link_train_cr()
734 vs = dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; in zynqmp_dp_link_train_cr()
864 memset(dp->train_set, 0, sizeof(dp->train_set)); in zynqmp_dp_train()
/linux-6.1.9/drivers/gpu/drm/gma500/
Dcdv_intel_dp.c266 uint8_t train_set[4]; member
1297 intel_dp->train_set[lane] = v | p; in cdv_intel_get_adjust_train()
1386 intel_dp->train_set, in cdv_intel_dplink_set_level()
1391 intel_dp->train_set[0], intel_dp->lane_count); in cdv_intel_dplink_set_level()
1491 memset(intel_dp->train_set, 0, 4); in cdv_intel_dp_start_link_train()
1502 intel_dp->train_set[0], in cdv_intel_dp_start_link_train()
1509 cdv_intel_dp_set_vswing_premph(encoder, intel_dp->train_set[0]); in cdv_intel_dp_start_link_train()
1530 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) in cdv_intel_dp_start_link_train()
1536 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { in cdv_intel_dp_start_link_train()
1542 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; in cdv_intel_dp_start_link_train()
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