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Searched refs:tiling_flags (Results 1 – 25 of 29) sorted by relevance

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/linux-6.1.9/drivers/gpu/drm/radeon/
Dradeon_object.c531 lobj->tiling_flags = bo->tiling_flags; in radeon_bo_list_validate()
536 lobj->tiling_flags = lobj->robj->tiling_flags; in radeon_bo_list_validate()
552 if (!bo->tiling_flags) in radeon_bo_get_surface_reg()
590 radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch, in radeon_bo_get_surface_reg()
612 uint32_t tiling_flags, uint32_t pitch) in radeon_bo_set_tiling_flags() argument
620 bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK; in radeon_bo_set_tiling_flags()
621 bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK; in radeon_bo_set_tiling_flags()
622 …mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TIL… in radeon_bo_set_tiling_flags()
623 …tilesplit = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK; in radeon_bo_set_tiling_flags()
624 …stilesplit = (tiling_flags >> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_STENCI… in radeon_bo_set_tiling_flags()
[all …]
Dradeon_fb.c136 u32 tiling_flags = 0; in radeonfb_create_pinned_object() local
163 tiling_flags = RADEON_TILING_MACRO; in radeonfb_create_pinned_object()
168 tiling_flags |= RADEON_TILING_SWAP_32BIT; in radeonfb_create_pinned_object()
171 tiling_flags |= RADEON_TILING_SWAP_16BIT; in radeonfb_create_pinned_object()
178 if (tiling_flags) { in radeonfb_create_pinned_object()
180 tiling_flags | RADEON_TILING_SURFACE, in radeonfb_create_pinned_object()
Dradeon_object.h158 u32 tiling_flags, u32 pitch);
160 u32 *tiling_flags, u32 *pitch);
Dr200.c221 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r200_packet0_check()
223 if (reloc->tiling_flags & RADEON_TILING_MICRO) in r200_packet0_check()
293 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r200_packet0_check()
295 if (reloc->tiling_flags & RADEON_TILING_MICRO) in r200_packet0_check()
Dr300.c718 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r300_packet0_check()
720 if (reloc->tiling_flags & RADEON_TILING_MICRO) in r300_packet0_check()
722 else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE) in r300_packet0_check()
787 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r300_packet0_check()
789 if (reloc->tiling_flags & RADEON_TILING_MICRO) in r300_packet0_check()
791 else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE) in r300_packet0_check()
872 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r300_packet0_check()
874 if (reloc->tiling_flags & RADEON_TILING_MICRO) in r300_packet0_check()
876 else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE) in r300_packet0_check()
Dradeon_legacy_crtc.c387 uint32_t tiling_flags; in radeon_crtc_do_set_base() local
465 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); in radeon_crtc_do_set_base()
467 if (tiling_flags & RADEON_TILING_MICRO) in radeon_crtc_do_set_base()
484 if (tiling_flags & RADEON_TILING_MACRO) { in radeon_crtc_do_set_base()
500 if (tiling_flags & RADEON_TILING_MACRO) { in radeon_crtc_do_set_base()
Devergreen_cs.c92 static u32 evergreen_cs_get_aray_mode(u32 tiling_flags) in evergreen_cs_get_aray_mode() argument
94 if (tiling_flags & RADEON_TILING_MACRO) in evergreen_cs_get_aray_mode()
96 else if (tiling_flags & RADEON_TILING_MICRO) in evergreen_cs_get_aray_mode()
1179 ib[idx] |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); in evergreen_cs_handle_reg()
1180 track->db_z_info |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); in evergreen_cs_handle_reg()
1181 if (reloc->tiling_flags & RADEON_TILING_MACRO) { in evergreen_cs_handle_reg()
1184 evergreen_tiling_fields(reloc->tiling_flags, in evergreen_cs_handle_reg()
1365 ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); in evergreen_cs_handle_reg()
1366 track->cb_color_info[tmp] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); in evergreen_cs_handle_reg()
1383 ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); in evergreen_cs_handle_reg()
[all …]
Datombios_crtc.c1146 uint32_t fb_format, fb_pitch_pixels, tiling_flags; in dce4_crtc_do_set_base() local
1183 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); in dce4_crtc_do_set_base()
1266 if (tiling_flags & RADEON_TILING_MACRO) { in dce4_crtc_do_set_base()
1267 evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split); in dce4_crtc_do_set_base()
1340 } else if (tiling_flags & RADEON_TILING_MICRO) in dce4_crtc_do_set_base()
1467 uint32_t fb_format, fb_pitch_pixels, tiling_flags; in avivo_crtc_do_set_base() local
1502 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); in avivo_crtc_do_set_base()
1578 if (tiling_flags & RADEON_TILING_MACRO) in avivo_crtc_do_set_base()
1580 else if (tiling_flags & RADEON_TILING_MICRO) in avivo_crtc_do_set_base()
1583 if (tiling_flags & RADEON_TILING_MACRO) in avivo_crtc_do_set_base()
[all …]
Dr100.c1291 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r100_reloc_pitch_offset()
1293 if (reloc->tiling_flags & RADEON_TILING_MICRO) { in r100_reloc_pitch_offset()
1633 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r100_packet0_check()
1635 if (reloc->tiling_flags & RADEON_TILING_MICRO) in r100_packet0_check()
1714 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r100_packet0_check()
1716 if (reloc->tiling_flags & RADEON_TILING_MICRO) in r100_packet0_check()
3091 uint32_t tiling_flags, uint32_t pitch, in r100_set_surface_reg() argument
3098 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO)) in r100_set_surface_reg()
3101 if (tiling_flags & RADEON_TILING_MACRO) in r100_set_surface_reg()
3104 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO)) in r100_set_surface_reg()
[all …]
Dr600_cs.c1041 if (reloc->tiling_flags & RADEON_TILING_MACRO) { in r600_cs_check_reg()
1140 if (reloc->tiling_flags & RADEON_TILING_MACRO) { in r600_cs_check_reg()
1143 } else if (reloc->tiling_flags & RADEON_TILING_MICRO) { in r600_cs_check_reg()
1474 u32 tiling_flags) in r600_check_texture_resource() argument
1496 if (tiling_flags & RADEON_TILING_MACRO) in r600_check_texture_resource()
1498 else if (tiling_flags & RADEON_TILING_MICRO) in r600_check_texture_resource()
1967 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r600_packet3_check()
1969 else if (reloc->tiling_flags & RADEON_TILING_MICRO) in r600_packet3_check()
1985 reloc->tiling_flags); in r600_packet3_check()
Dradeon_gem.c588 r = radeon_bo_set_tiling_flags(robj, args->tiling_flags, args->pitch); in radeon_gem_set_tiling_ioctl()
609 radeon_bo_get_tiling_flags(rbo, &args->tiling_flags, &args->pitch); in radeon_gem_get_tiling_ioctl()
Dradeon_vm.c147 list[0].tiling_flags = 0; in radeon_vm_get_bos()
159 list[idx].tiling_flags = 0; in radeon_vm_get_bos()
Dradeon_display.c491 uint32_t tiling_flags, pitch_pixels; in radeon_crtc_page_flip_target() local
543 radeon_bo_get_tiling_flags(new_rbo, &tiling_flags, NULL); in radeon_crtc_page_flip_target()
551 if (tiling_flags & RADEON_TILING_MACRO) { in radeon_crtc_page_flip_target()
Dradeon.h355 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
464 uint32_t tiling_flags; member
495 u32 tiling_flags; member
1964 uint32_t tiling_flags, uint32_t pitch,
/linux-6.1.9/drivers/gpu/drm/amd/amdgpu/
Damdgpu_display.c165 u64 tiling_flags; in amdgpu_display_crtc_page_flip_target() local
220 amdgpu_bo_get_tiling_flags(new_abo, &tiling_flags); in amdgpu_display_crtc_page_flip_target()
675 if (!afb->tiling_flags || !AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE)) { in convert_tiling_flags_to_modifier()
678 int swizzle = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE); in convert_tiling_flags_to_modifier()
687 uint32_t dcc_offset = AMDGPU_TILING_GET(afb->tiling_flags, DCC_OFFSET_256B); in convert_tiling_flags_to_modifier()
769 AMD_FMT_MOD_SET(TILE, AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE)) | in convert_tiling_flags_to_modifier()
776 bool dcc_i64b = AMDGPU_TILING_GET(afb->tiling_flags, DCC_INDEPENDENT_64B) != 0; in convert_tiling_flags_to_modifier()
799 AMDGPU_TILING_GET(afb->tiling_flags, DCC_PITCH_MAX) + 1; in convert_tiling_flags_to_modifier()
857 if (AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE) == 0) in check_tiling_flags_gfx6()
860 micro_tile_mode = AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE); in check_tiling_flags_gfx6()
[all …]
Damdgpu_object.h115 u64 tiling_flags; member
308 int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags);
309 void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags);
Damdgpu_object.c1100 int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags) in amdgpu_bo_set_tiling_flags() argument
1107 AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6) in amdgpu_bo_set_tiling_flags()
1111 ubo->tiling_flags = tiling_flags; in amdgpu_bo_set_tiling_flags()
1123 void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags) in amdgpu_bo_get_tiling_flags() argument
1131 if (tiling_flags) in amdgpu_bo_get_tiling_flags()
1132 *tiling_flags = ubo->tiling_flags; in amdgpu_bo_get_tiling_flags()
Ddce_v6_0.c1817 uint64_t fb_location, tiling_flags; in dce_v6_0_crtc_do_set_base() local
1853 amdgpu_bo_get_tiling_flags(abo, &tiling_flags); in dce_v6_0_crtc_do_set_base()
1936 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { in dce_v6_0_crtc_do_set_base()
1939 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in dce_v6_0_crtc_do_set_base()
1940 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); in dce_v6_0_crtc_do_set_base()
1941 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); in dce_v6_0_crtc_do_set_base()
1942 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); in dce_v6_0_crtc_do_set_base()
1943 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); in dce_v6_0_crtc_do_set_base()
1951 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { in dce_v6_0_crtc_do_set_base()
1955 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); in dce_v6_0_crtc_do_set_base()
Ddce_v8_0.c1787 uint64_t fb_location, tiling_flags; in dce_v8_0_crtc_do_set_base() local
1824 amdgpu_bo_get_tiling_flags(abo, &tiling_flags); in dce_v8_0_crtc_do_set_base()
1827 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); in dce_v8_0_crtc_do_set_base()
1909 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { in dce_v8_0_crtc_do_set_base()
1912 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in dce_v8_0_crtc_do_set_base()
1913 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); in dce_v8_0_crtc_do_set_base()
1914 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); in dce_v8_0_crtc_do_set_base()
1915 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); in dce_v8_0_crtc_do_set_base()
1916 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); in dce_v8_0_crtc_do_set_base()
1925 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { in dce_v8_0_crtc_do_set_base()
Ddce_v10_0.c1858 uint64_t fb_location, tiling_flags; in dce_v10_0_crtc_do_set_base() local
1895 amdgpu_bo_get_tiling_flags(abo, &tiling_flags); in dce_v10_0_crtc_do_set_base()
1898 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); in dce_v10_0_crtc_do_set_base()
1988 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { in dce_v10_0_crtc_do_set_base()
1991 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in dce_v10_0_crtc_do_set_base()
1992 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); in dce_v10_0_crtc_do_set_base()
1993 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); in dce_v10_0_crtc_do_set_base()
1994 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); in dce_v10_0_crtc_do_set_base()
1995 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); in dce_v10_0_crtc_do_set_base()
2008 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { in dce_v10_0_crtc_do_set_base()
Ddce_v11_0.c1900 uint64_t fb_location, tiling_flags; in dce_v11_0_crtc_do_set_base() local
1937 amdgpu_bo_get_tiling_flags(abo, &tiling_flags); in dce_v11_0_crtc_do_set_base()
1940 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); in dce_v11_0_crtc_do_set_base()
2030 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { in dce_v11_0_crtc_do_set_base()
2033 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in dce_v11_0_crtc_do_set_base()
2034 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); in dce_v11_0_crtc_do_set_base()
2035 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); in dce_v11_0_crtc_do_set_base()
2036 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); in dce_v11_0_crtc_do_set_base()
2037 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); in dce_v11_0_crtc_do_set_base()
2050 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { in dce_v11_0_crtc_do_set_base()
Damdgpu_mode.h303 uint64_t tiling_flags; member
/linux-6.1.9/drivers/gpu/drm/amd/display/amdgpu_dm/
Damdgpu_dm_plane.c167 uint64_t tiling_flags) in fill_gfx8_tiling_info_from_flags() argument
170 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) { in fill_gfx8_tiling_info_from_flags()
173 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in fill_gfx8_tiling_info_from_flags()
174 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); in fill_gfx8_tiling_info_from_flags()
175 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); in fill_gfx8_tiling_info_from_flags()
176 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); in fill_gfx8_tiling_info_from_flags()
177 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); in fill_gfx8_tiling_info_from_flags()
189 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) in fill_gfx8_tiling_info_from_flags()
195 AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); in fill_gfx8_tiling_info_from_flags()
757 const uint64_t tiling_flags, in fill_plane_buffer_attributes() argument
[all …]
Damdgpu_dm_plane.h46 const uint64_t tiling_flags,
/linux-6.1.9/include/uapi/drm/
Dradeon_drm.h858 __u32 tiling_flags; member
864 __u32 tiling_flags; member

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