Searched refs:tile_mode_array (Results 1 – 13 of 13) sorted by relevance
501 value = rdev->config.cik.tile_mode_array; in radeon_info_ioctl()504 value = rdev->config.si.tile_mode_array; in radeon_info_ioctl()
1306 num_banks = (rdev->config.si.tile_mode_array[index] >> 20) & 0x3; in dce4_crtc_do_set_base()1347 u32 pipe_config = (rdev->config.cik.tile_mode_array[10] >> 6) & 0x1f; in dce4_crtc_do_set_base()
2185 uint32_t tile_mode_array[32]; member2216 uint32_t tile_mode_array[32]; member
2490 u32 *tile = rdev->config.si.tile_mode_array; in si_tiling_mode_table_init()2492 ARRAY_SIZE(rdev->config.si.tile_mode_array); in si_tiling_mode_table_init()
2322 u32 *tile = rdev->config.cik.tile_mode_array; in cik_tiling_mode_table_init()2325 ARRAY_SIZE(rdev->config.cik.tile_mode_array); in cik_tiling_mode_table_init()
166 uint32_t tile_mode_array[32]; member
399 const u32 num_tile_mode_states = ARRAY_SIZE(adev->gfx.config.tile_mode_array); in gfx_v6_0_tiling_mode_table_init()402 memset(adev->gfx.config.tile_mode_array, 0, sizeof(adev->gfx.config.tile_mode_array)); in gfx_v6_0_tiling_mode_table_init()403 tilemode = adev->gfx.config.tile_mode_array; in gfx_v6_0_tiling_mode_table_init()
2903 config->tile_config_ptr = adev->gfx.config.tile_mode_array; in amdgpu_amdkfd_get_tile_config()2905 ARRAY_SIZE(adev->gfx.config.tile_mode_array); in amdgpu_amdkfd_get_tile_config()
1193 return adev->gfx.config.tile_mode_array[idx]; in cik_get_register_value()
818 return adev->gfx.config.tile_mode_array[idx]; in vi_get_register_value()
1233 return adev->gfx.config.tile_mode_array[idx]; in si_get_register_value()
1026 ARRAY_SIZE(adev->gfx.config.tile_mode_array); in gfx_v7_0_tiling_mode_table_init()1032 tile = adev->gfx.config.tile_mode_array; in gfx_v7_0_tiling_mode_table_init()
2103 const u32 num_tile_mode_states = ARRAY_SIZE(adev->gfx.config.tile_mode_array); in gfx_v8_0_tiling_mode_table_init()2107 modearray = adev->gfx.config.tile_mode_array; in gfx_v8_0_tiling_mode_table_init()