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Searched refs:tg_mask (Results 1 – 25 of 25) sorted by relevance

/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn201/
Ddcn201_optc.c39 optc1->tg_shift->field_name, optc1->tg_mask->field_name
195 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; in dcn201_timing_generator_init()
196 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1; in dcn201_timing_generator_init()
Ddcn201_resource.c513 static const struct dcn_optc_mask tg_mask = { variable
771 tgn10->tg_mask = &tg_mask; in dcn201_timing_generator_create()
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn314/
Ddcn314_optc.c43 optc1->tg_shift->field_name, optc1->tg_mask->field_name
266 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; in dcn314_timing_generator_init()
267 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1; in dcn314_timing_generator_init()
Ddcn314_resource.c1106 tgn10->tg_mask = &optc_mask; in dcn31_timing_generator_create()
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn31/
Ddcn31_optc.c41 optc1->tg_shift->field_name, optc1->tg_mask->field_name
301 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; in dcn31_timing_generator_init()
302 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1; in dcn31_timing_generator_init()
Ddcn31_resource.c1080 tgn10->tg_mask = &optc_mask; in dcn31_timing_generator_create()
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn32/
Ddcn32_optc.c43 optc1->tg_shift->field_name, optc1->tg_mask->field_name
319 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; in dcn32_timing_generator_init()
320 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1; in dcn32_timing_generator_init()
Ddcn32_resource.c1021 tgn10->tg_mask = &optc_mask; in dcn32_timing_generator_create()
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn30/
Ddcn30_optc.c42 optc1->tg_shift->field_name, optc1->tg_mask->field_name
360 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; in dcn30_timing_generator_init()
361 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1; in dcn30_timing_generator_init()
Ddcn30_resource.c911 tgn10->tg_mask = &optc_mask; in dcn30_timing_generator_create()
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_optc.c38 optc1->tg_shift->field_name, optc1->tg_mask->field_name
563 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; in dcn20_timing_generator_init()
564 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1; in dcn20_timing_generator_init()
Ddcn20_resource.c511 static const struct dcn_optc_mask tg_mask = { variable
908 tgn10->tg_mask = &tg_mask; in dcn20_timing_generator_create()
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_optc.c39 optc1->tg_shift->field_name, optc1->tg_mask->field_name
289 if (REG(OPTC_DATA_FORMAT_CONTROL) && optc1->tg_mask->OPTC_DATA_FORMAT != 0) { in optc1_program_timing()
300 if (optc1->tg_mask->OTG_H_TIMING_DIV_MODE != 0) { in optc1_program_timing()
1582 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; in dcn10_timing_generator_init()
1583 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1; in dcn10_timing_generator_init()
Ddcn10_resource.c402 static const struct dcn_optc_mask tg_mask = { variable
724 tgn10->tg_mask = &tg_mask; in dcn10_timing_generator_create()
Ddcn10_optc.h542 const struct dcn_optc_mask *tg_mask; member
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/
Ddcn32_clk_mgr.c241 uint32_t tg_mask = 0; in dcn32_update_clocks_update_dtb_dto() local
250 !(tg_mask & (1 << pipe_ctx->stream_res.tg->inst))) { in dcn32_update_clocks_update_dtb_dto()
251 tg_mask |= (1 << pipe_ctx->stream_res.tg->inst); in dcn32_update_clocks_update_dtb_dto()
/linux-6.1.9/drivers/net/ethernet/mscc/
Docelot_vcap.c46 u32 tg_mask; /* Current type-group mask */ member
199 data->tg_mask = 0; in vcap_data_offset_get()
203 data->tg_mask |= GENMASK(offset + width - 1, offset); in vcap_data_offset_get()
365 data.tg = (data.tg & ~data.tg_mask); in is2_entry_set()
688 data.tg = (data.tg & ~data.tg_mask); in is1_entry_set()
826 data.tg = (data.tg & ~data.tg_mask); in es0_entry_set()
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn21/
Ddcn21_resource.c274 static const struct dcn_optc_mask tg_mask = { variable
1088 tgn10->tg_mask = &tg_mask; in dcn21_timing_generator_create()
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dml/dcn30/
Ddcn30_fpu.c44 optc1->tg_shift->field_name, optc1->tg_mask->field_name
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn302/
Ddcn302_resource.c621 tgn10->tg_mask = &optc_mask; in dcn302_timing_generator_create()
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn303/
Ddcn303_resource.c576 tgn10->tg_mask = &optc_mask; in dcn303_timing_generator_create()
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn301/
Ddcn301_resource.c874 tgn10->tg_mask = &optc_mask; in dcn301_timing_generator_create()
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn315/
Ddcn315_resource.c1076 tgn10->tg_mask = &optc_mask; in dcn31_timing_generator_create()
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn316/
Ddcn316_resource.c1075 tgn10->tg_mask = &optc_mask; in dcn31_timing_generator_create()
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn321/
Ddcn321_resource.c1020 tgn10->tg_mask = &optc_mask; in dcn321_timing_generator_create()