| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn32/ |
| D | dcn32_dpp.c | 149 const struct dcn3_dpp_registers *tf_regs, in dpp32_construct() argument
159 dpp->tf_regs = tf_regs; in dpp32_construct()
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| D | dcn32_dpp.h | 34 const struct dcn3_dpp_registers *tf_regs,
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn201/ |
| D | dcn201_dpp.h | 60 const struct dcn201_dpp_registers *tf_regs; member
79 const struct dcn201_dpp_registers *tf_regs,
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| D | dcn201_dpp.c | 35 dpp->tf_regs->reg
296 const struct dcn201_dpp_registers *tf_regs, in dpp201_construct() argument
306 dpp->tf_regs = tf_regs; in dpp201_construct()
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| D | dcn201_resource.c | 463 #define tf_regs(id)\ macro
468 static const struct dcn201_dpp_registers tf_regs[] = { variable
469 tf_regs(0),
470 tf_regs(1),
471 tf_regs(2),
472 tf_regs(3),
637 &tf_regs[inst], &tf_shift, &tf_mask)) in dcn201_dpp_create()
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn20/ |
| D | dcn20_dpp.c | 42 dpp->tf_regs->reg
407 const struct dcn2_dpp_registers *tf_regs, in dpp2_construct() argument
417 dpp->tf_regs = tf_regs; in dpp2_construct()
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| D | dcn20_resource.c | 409 #define tf_regs(id)\ macro
415 static const struct dcn2_dpp_registers tf_regs[] = { variable
416 tf_regs(0),
417 tf_regs(1),
418 tf_regs(2),
419 tf_regs(3),
420 tf_regs(4),
421 tf_regs(5),
755 &tf_regs[inst], &tf_shift, &tf_mask)) in dcn20_dpp_create()
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| D | dcn20_dpp.h | 681 const struct dcn2_dpp_registers *tf_regs; member
771 const struct dcn2_dpp_registers *tf_regs,
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| D | dcn20_dpp_cm.c | 37 dpp->tf_regs->reg
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn10/ |
| D | dcn10_dpp.c | 42 dpp->tf_regs->reg
562 const struct dcn_dpp_registers *tf_regs, in dpp1_construct() argument
572 dpp->tf_regs = tf_regs; in dpp1_construct()
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| D | dcn10_resource.c | 344 #define tf_regs(id)\ macro
349 static const struct dcn_dpp_registers tf_regs[] = { variable
350 tf_regs(0),
351 tf_regs(1),
352 tf_regs(2),
353 tf_regs(3),
588 &tf_regs[inst], &tf_shift, &tf_mask); in dcn10_dpp_create()
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| D | dcn10_dpp_dscl.c | 47 dpp->tf_regs->reg
166 if (dpp->tf_regs->DSCL_MEM_PWR_CTRL) { in dpp1_power_on_dscl()
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| D | dcn10_dpp_cm.c | 43 dpp->tf_regs->reg
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| D | dcn10_dpp.h | 1355 const struct dcn_dpp_registers *tf_regs; member
1517 const struct dcn_dpp_registers *tf_regs,
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn21/ |
| D | dcn21_resource.c | 431 #define tf_regs(id)\ macro
437 static const struct dcn2_dpp_registers tf_regs[] = { variable
438 tf_regs(0),
439 tf_regs(1),
440 tf_regs(2),
441 tf_regs(3),
512 &tf_regs[inst], &tf_shift, &tf_mask)) in dcn21_dpp_create()
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn30/ |
| D | dcn30_dpp.c | 34 dpp->tf_regs->reg
1471 const struct dcn3_dpp_registers *tf_regs, in dpp3_construct() argument
1481 dpp->tf_regs = tf_regs; in dpp3_construct()
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| D | dcn30_dpp.h | 561 const struct dcn3_dpp_registers *tf_regs; member
580 const struct dcn3_dpp_registers *tf_regs,
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| D | dcn30_dpp_cm.c | 34 dpp->tf_regs->reg
|