Home
last modified time | relevance | path

Searched refs:tCCS_min (Results 1 – 9 of 9) sorted by relevance

/linux-6.1.9/drivers/mtd/nand/raw/
Dnand_timings.c28 .tCCS_min = 500000,
73 .tCCS_min = 500000,
118 .tCCS_min = 500000,
163 .tCCS_min = 500000,
208 .tCCS_min = 500000,
253 .tCCS_min = 500000,
301 .tCCS_min = 500000,
343 .tCCS_min = 500000,
385 .tCCS_min = 500000,
427 .tCCS_min = 500000,
[all …]
Darasan-nand-controller.c1008 if (conf->timings.nvddr.tCCS_min <= 100000) in anfc_setup_interface()
1010 else if (conf->timings.nvddr.tCCS_min <= 200000) in anfc_setup_interface()
1012 else if (conf->timings.nvddr.tCCS_min <= 300000) in anfc_setup_interface()
Dnand_legacy.c373 ndelay(sdr->tCCS_min / 1000); in nand_ccs_delay()
Dmarvell_nand.c2404 nfc_tmg.tWHR = TO_CYCLES(max_t(int, sdr->tWHR_min, sdr->tCCS_min), in marvell_nfc_setup_interface()
2406 nfc_tmg.tRHW = TO_CYCLES(max_t(int, sdr->tRHW_min, sdr->tCCS_min), in marvell_nfc_setup_interface()
Ddenali.c824 we_2_re = DIV_ROUND_UP(max(timings->tCCS_min, timings->tWHR_min), t_x); in denali_setup_interface()
Drenesas-nand-controller.c914 TIM_SEQ0_TCCS(TO_CYCLES64(sdr->tCCS_min, period_ns)) | in rnandc_setup_interface()
Dnand_base.c1338 NAND_COMMON_TIMING_NS(conf, tCCS_min)), in nand_change_read_column_op()
1645 NAND_OP_ADDR(2, addrs, NAND_COMMON_TIMING_NS(conf, tCCS_min)), in nand_change_write_column_op()
Dcadence-nand-controller.c2469 tccs_cnt = calc_cycl((sdr->tCCS_min + if_skew), clk_period); in cadence_nand_setup_interface()
/linux-6.1.9/include/linux/mtd/
Drawnand.h436 u32 tCCS_min; member
525 u32 tCCS_min; member