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Searched refs:smu_wm_set (Results 1 – 10 of 10) sorted by relevance

/linux-6.1.9/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/
Ddcn316_clk_mgr.c414 struct dcn316_watermarks *table = clk_mgr_dcn316->smu_wm_set.wm_set; in dcn316_notify_wm_ranges()
419 if (!table || clk_mgr_dcn316->smu_wm_set.mc_address.quad_part == 0) in dcn316_notify_wm_ranges()
427 clk_mgr_dcn316->smu_wm_set.mc_address.high_part); in dcn316_notify_wm_ranges()
429 clk_mgr_dcn316->smu_wm_set.mc_address.low_part); in dcn316_notify_wm_ranges()
634 clk_mgr->smu_wm_set.wm_set = (struct dcn316_watermarks *)dm_helpers_allocate_gpu_mem( in dcn316_clk_mgr_construct()
638 &clk_mgr->smu_wm_set.mc_address.quad_part); in dcn316_clk_mgr_construct()
640 if (!clk_mgr->smu_wm_set.wm_set) { in dcn316_clk_mgr_construct()
641 clk_mgr->smu_wm_set.wm_set = &dummy_wms; in dcn316_clk_mgr_construct()
642 clk_mgr->smu_wm_set.mc_address.quad_part = 0; in dcn316_clk_mgr_construct()
644 ASSERT(clk_mgr->smu_wm_set.wm_set); in dcn316_clk_mgr_construct()
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Ddcn316_clk_mgr.h39 struct dcn316_smu_watermark_set smu_wm_set; member
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/
Dvg_clk_mgr.c448 struct watermarks *table = clk_mgr_vgh->smu_wm_set.wm_set; in vg_notify_wm_ranges()
453 if (!table || clk_mgr_vgh->smu_wm_set.mc_address.quad_part == 0) in vg_notify_wm_ranges()
461 clk_mgr_vgh->smu_wm_set.mc_address.high_part); in vg_notify_wm_ranges()
463 clk_mgr_vgh->smu_wm_set.mc_address.low_part); in vg_notify_wm_ranges()
664 clk_mgr->smu_wm_set.wm_set = (struct watermarks *)dm_helpers_allocate_gpu_mem( in vg_clk_mgr_construct()
668 &clk_mgr->smu_wm_set.mc_address.quad_part); in vg_clk_mgr_construct()
670 if (!clk_mgr->smu_wm_set.wm_set) { in vg_clk_mgr_construct()
671 clk_mgr->smu_wm_set.wm_set = &dummy_wms; in vg_clk_mgr_construct()
672 clk_mgr->smu_wm_set.mc_address.quad_part = 0; in vg_clk_mgr_construct()
674 ASSERT(clk_mgr->smu_wm_set.wm_set); in vg_clk_mgr_construct()
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Dvg_clk_mgr.h42 struct smu_watermark_set smu_wm_set; member
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/
Ddcn31_clk_mgr.c478 struct dcn31_watermarks *table = clk_mgr_dcn31->smu_wm_set.wm_set; in dcn31_notify_wm_ranges()
483 if (!table || clk_mgr_dcn31->smu_wm_set.mc_address.quad_part == 0) in dcn31_notify_wm_ranges()
491 clk_mgr_dcn31->smu_wm_set.mc_address.high_part); in dcn31_notify_wm_ranges()
493 clk_mgr_dcn31->smu_wm_set.mc_address.low_part); in dcn31_notify_wm_ranges()
688 clk_mgr->smu_wm_set.wm_set = (struct dcn31_watermarks *)dm_helpers_allocate_gpu_mem( in dcn31_clk_mgr_construct()
692 &clk_mgr->smu_wm_set.mc_address.quad_part); in dcn31_clk_mgr_construct()
694 if (!clk_mgr->smu_wm_set.wm_set) { in dcn31_clk_mgr_construct()
695 clk_mgr->smu_wm_set.wm_set = &dummy_wms; in dcn31_clk_mgr_construct()
696 clk_mgr->smu_wm_set.mc_address.quad_part = 0; in dcn31_clk_mgr_construct()
698 ASSERT(clk_mgr->smu_wm_set.wm_set); in dcn31_clk_mgr_construct()
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Ddcn31_clk_mgr.h39 struct dcn31_smu_watermark_set smu_wm_set; member
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/
Ddcn315_clk_mgr.c422 struct dcn315_watermarks *table = clk_mgr_dcn315->smu_wm_set.wm_set; in dcn315_notify_wm_ranges()
427 if (!table || clk_mgr_dcn315->smu_wm_set.mc_address.quad_part == 0) in dcn315_notify_wm_ranges()
435 clk_mgr_dcn315->smu_wm_set.mc_address.high_part); in dcn315_notify_wm_ranges()
437 clk_mgr_dcn315->smu_wm_set.mc_address.low_part); in dcn315_notify_wm_ranges()
625 clk_mgr->smu_wm_set.wm_set = (struct dcn315_watermarks *)dm_helpers_allocate_gpu_mem( in dcn315_clk_mgr_construct()
629 &clk_mgr->smu_wm_set.mc_address.quad_part); in dcn315_clk_mgr_construct()
631 if (!clk_mgr->smu_wm_set.wm_set) { in dcn315_clk_mgr_construct()
632 clk_mgr->smu_wm_set.wm_set = &dummy_wms; in dcn315_clk_mgr_construct()
633 clk_mgr->smu_wm_set.mc_address.quad_part = 0; in dcn315_clk_mgr_construct()
635 ASSERT(clk_mgr->smu_wm_set.wm_set); in dcn315_clk_mgr_construct()
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Ddcn315_clk_mgr.h39 struct dcn315_smu_watermark_set smu_wm_set; member
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/
Ddcn314_clk_mgr.c497 struct dcn314_watermarks *table = clk_mgr_dcn314->smu_wm_set.wm_set; in dcn314_notify_wm_ranges()
502 if (!table || clk_mgr_dcn314->smu_wm_set.mc_address.quad_part == 0) in dcn314_notify_wm_ranges()
510 clk_mgr_dcn314->smu_wm_set.mc_address.high_part); in dcn314_notify_wm_ranges()
512 clk_mgr_dcn314->smu_wm_set.mc_address.low_part); in dcn314_notify_wm_ranges()
738 clk_mgr->smu_wm_set.wm_set = (struct dcn314_watermarks *)dm_helpers_allocate_gpu_mem( in dcn314_clk_mgr_construct()
742 &clk_mgr->smu_wm_set.mc_address.quad_part); in dcn314_clk_mgr_construct()
744 if (!clk_mgr->smu_wm_set.wm_set) { in dcn314_clk_mgr_construct()
745 clk_mgr->smu_wm_set.wm_set = &dummy_wms; in dcn314_clk_mgr_construct()
746 clk_mgr->smu_wm_set.mc_address.quad_part = 0; in dcn314_clk_mgr_construct()
748 ASSERT(clk_mgr->smu_wm_set.wm_set); in dcn314_clk_mgr_construct()
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Ddcn314_clk_mgr.h40 struct dcn314_smu_watermark_set smu_wm_set; member