Searched refs:smu_v11_0_set_hard_freq_limited_range (Results 1 – 4 of 4) sorted by relevance
/linux-6.1.9/drivers/gpu/drm/amd/pm/swsmu/inc/ |
D | smu_v11_0.h | 262 int smu_v11_0_set_hard_freq_limited_range(struct smu_context *smu,
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/linux-6.1.9/drivers/gpu/drm/amd/pm/swsmu/smu11/ |
D | navi10_ppt.c | 1832 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, max_freq); in navi10_pre_display_config_changed() 2103 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0); in navi10_notify_smc_display_config() 2317 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, max_memory_clock, 0); in navi10_display_disable_memory_clock_switch() 2319 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_memory_clock, 0); in navi10_display_disable_memory_clock_switch() 2785 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, uclk_min); in navi10_umc_hybrid_cdr_workaround() 2790 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, uclk_max); in navi10_umc_hybrid_cdr_workaround()
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D | smu_v11_0.c | 1117 ret = smu_v11_0_set_hard_freq_limited_range(smu, clk_select, clk_freq, 0); in smu_v11_0_display_clock_voltage_request() 1812 int smu_v11_0_set_hard_freq_limited_range(struct smu_context *smu, in smu_v11_0_set_hard_freq_limited_range() function
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D | sienna_cichlid_ppt.c | 1528 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, max_freq); in sienna_cichlid_pre_display_config_changed() 1800 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0); in sienna_cichlid_notify_smc_display_config() 2060 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, max_memory_clock, 0); in sienna_cichlid_display_disable_memory_clock_switch() 2062 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_memory_clock, 0); in sienna_cichlid_display_disable_memory_clock_switch()
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