/linux-6.1.9/drivers/gpu/drm/amd/pm/swsmu/smu13/ |
D | aldebaran_ppt.c | 316 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) { in aldebaran_set_default_dpm_table() 332 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) { in aldebaran_set_default_dpm_table() 351 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { in aldebaran_set_default_dpm_table() 367 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) { in aldebaran_set_default_dpm_table() 698 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) in aldebaran_get_current_clk_freq_by_table() 704 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) in aldebaran_get_current_clk_freq_by_table() 710 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) in aldebaran_get_current_clk_freq_by_table() 716 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) in aldebaran_get_current_clk_freq_by_table() 722 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) in aldebaran_get_current_clk_freq_by_table() 943 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) && in aldebaran_upload_dpm_level() [all …]
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D | smu_v13_0.c | 877 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) && in smu_v13_0_notify_display_change() 935 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { in smu_v13_0_init_max_sustainable_clocks() 946 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) { in smu_v13_0_init_max_sustainable_clocks() 957 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { in smu_v13_0_init_max_sustainable_clocks() 1005 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) in smu_v13_0_get_current_power_limit() 1035 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) { in smu_v13_0_set_power_limit() 1063 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_ACDC_BIT)) in smu_v13_0_process_pending_interrupt() 1125 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) || in smu_v13_0_display_clock_voltage_request() 1126 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { in smu_v13_0_display_clock_voltage_request() 1167 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT)) in smu_v13_0_get_fan_control_mode() [all …]
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D | smu_v13_0_7_ppt.c | 555 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) { in smu_v13_0_7_set_default_dpm_table() 571 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) { in smu_v13_0_7_set_default_dpm_table() 587 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { in smu_v13_0_7_set_default_dpm_table() 603 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) { in smu_v13_0_7_set_default_dpm_table() 619 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_VCLK_BIT)) { in smu_v13_0_7_set_default_dpm_table() 635 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCLK_BIT)) { in smu_v13_0_7_set_default_dpm_table() 1680 .feature_is_enabled = smu_cmn_feature_is_enabled,
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D | smu_v13_0_0_ppt.c | 526 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) { in smu_v13_0_0_set_default_dpm_table() 542 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) { in smu_v13_0_0_set_default_dpm_table() 575 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { in smu_v13_0_0_set_default_dpm_table() 591 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) { in smu_v13_0_0_set_default_dpm_table() 607 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_VCLK_BIT)) { in smu_v13_0_0_set_default_dpm_table() 623 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCLK_BIT)) { in smu_v13_0_0_set_default_dpm_table() 1997 .feature_is_enabled = smu_cmn_feature_is_enabled,
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D | smu_v13_0_4_ppt.c | 715 return smu_cmn_feature_is_enabled(smu, feature_id); in smu_v13_0_4_clk_dpm_is_enabled()
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D | smu_v13_0_5_ppt.c | 715 return smu_cmn_feature_is_enabled(smu, feature_id); in smu_v13_0_5_clk_dpm_is_enabled()
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D | yellow_carp_ppt.c | 841 return smu_cmn_feature_is_enabled(smu, feature_id); in yellow_carp_clk_dpm_is_enabled()
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/linux-6.1.9/drivers/gpu/drm/amd/pm/swsmu/smu11/ |
D | navi10_ppt.c | 971 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) { in navi10_set_default_dpm_table() 989 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) { in navi10_set_default_dpm_table() 1007 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { in navi10_set_default_dpm_table() 1025 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) { in navi10_set_default_dpm_table() 1043 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) { in navi10_set_default_dpm_table() 1061 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { in navi10_set_default_dpm_table() 1079 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { in navi10_set_default_dpm_table() 1097 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { in navi10_set_default_dpm_table() 1115 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { in navi10_set_default_dpm_table() 1140 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) { in navi10_dpm_set_vcn_enable() [all …]
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D | arcturus_ppt.c | 336 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) { in arcturus_set_default_dpm_table() 354 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) { in arcturus_set_default_dpm_table() 372 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { in arcturus_set_default_dpm_table() 390 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) { in arcturus_set_default_dpm_table() 719 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) in arcturus_get_current_clk_freq_by_table() 725 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) in arcturus_get_current_clk_freq_by_table() 731 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) in arcturus_get_current_clk_freq_by_table() 737 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_DPM_BIT)) in arcturus_get_current_clk_freq_by_table() 743 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_DPM_BIT)) in arcturus_get_current_clk_freq_by_table() 957 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) && in arcturus_upload_dpm_level() [all …]
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D | smu_v11_0.c | 811 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) && in smu_v11_0_notify_display_change() 869 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { in smu_v11_0_init_max_sustainable_clocks() 880 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) { in smu_v11_0_init_max_sustainable_clocks() 891 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { in smu_v11_0_init_max_sustainable_clocks() 939 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) in smu_v11_0_get_current_power_limit() 975 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) { in smu_v11_0_set_power_limit() 1019 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_ACDC_BIT)) in smu_v11_0_process_pending_interrupt() 1087 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) || in smu_v11_0_display_clock_voltage_request() 1088 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { in smu_v11_0_display_clock_voltage_request() 1158 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT)) in smu_v11_0_get_fan_control_mode() [all …]
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D | sienna_cichlid_ppt.c | 935 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) { in sienna_cichlid_set_default_dpm_table() 953 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) { in sienna_cichlid_set_default_dpm_table() 971 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { in sienna_cichlid_set_default_dpm_table() 989 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) { in sienna_cichlid_set_default_dpm_table() 1011 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) { in sienna_cichlid_set_default_dpm_table() 1033 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) { in sienna_cichlid_set_default_dpm_table() 1052 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { in sienna_cichlid_set_default_dpm_table() 1070 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { in sienna_cichlid_set_default_dpm_table() 1088 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { in sienna_cichlid_set_default_dpm_table() 1106 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { in sienna_cichlid_set_default_dpm_table() [all …]
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D | vangogh_ppt.c | 906 if (!smu_cmn_feature_is_enabled(smu, feature_id)) in vangogh_clk_dpm_is_enabled() 1341 if (!smu_cmn_feature_is_enabled(smu, clk_feature_map[i].feature)) in vangogh_unforce_dpm_levels() 2140 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) && in vangogh_post_smu_init() 2301 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) { in vangogh_set_power_limit() 2439 .feature_is_enabled = smu_cmn_feature_is_enabled,
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/linux-6.1.9/drivers/gpu/drm/amd/pm/swsmu/ |
D | smu_cmn.h | 57 int smu_cmn_feature_is_enabled(struct smu_context *smu,
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D | smu_cmn.c | 513 int smu_cmn_feature_is_enabled(struct smu_context *smu, in smu_cmn_feature_is_enabled() function 574 if (!smu_cmn_feature_is_enabled(smu, feature_id)) in smu_cmn_clk_dpm_is_enabled()
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/linux-6.1.9/drivers/gpu/drm/amd/pm/swsmu/smu12/ |
D | renoir_ppt.c | 655 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) { in renoir_dpm_set_vcn_enable() 661 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) { in renoir_dpm_set_vcn_enable() 676 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) { in renoir_dpm_set_jpeg_enable() 682 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) { in renoir_dpm_set_jpeg_enable() 735 if (!smu_cmn_feature_is_enabled(smu, clk_feature_map[i].feature)) in renoir_unforce_dpm_levels() 1446 .feature_is_enabled = smu_cmn_feature_is_enabled,
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