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Searched refs:smc_state_table (Results 1 – 25 of 25) sorted by relevance

/linux-6.1.9/drivers/gpu/drm/amd/pm/powerplay/smumgr/
Dtonga_smumgr.c530 smu_data->smc_state_table.LinkLevelCount = in tonga_populate_smc_link_level()
700 SMU72_Discrete_GraphicsLevel *levels = smu_data->smc_state_table.GraphicsLevel; in tonga_populate_all_graphic_levels()
713 &(smu_data->smc_state_table.GraphicsLevel[i])); in tonga_populate_all_graphic_levels()
719 smu_data->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0; in tonga_populate_all_graphic_levels()
723 smu_data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1; in tonga_populate_all_graphic_levels()
727 smu_data->smc_state_table.GraphicsLevel[dpm_table->sclk_table.count-1].DisplayWatermark = in tonga_populate_all_graphic_levels()
730 smu_data->smc_state_table.GraphicsDpmLevelCount = in tonga_populate_all_graphic_levels()
741 smu_data->smc_state_table.GraphicsLevel[i].pcieDpmLevel = in tonga_populate_all_graphic_levels()
771 smu_data->smc_state_table.GraphicsLevel[i].pcieDpmLevel = highest_pcie_level_enabled; in tonga_populate_all_graphic_levels()
774 smu_data->smc_state_table.GraphicsLevel[0].pcieDpmLevel = lowest_pcie_level_enabled; in tonga_populate_all_graphic_levels()
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Dfiji_smumgr.c490 SMU73_Discrete_DpmTable *dpm_table = &(smu_data->smc_state_table); in fiji_populate_bapm_parameters_in_dpm_table()
847 smu_data->smc_state_table.LinkLevelCount = in fiji_populate_smc_link_level()
1015 smu_data->smc_state_table.GraphicsLevel; in fiji_populate_all_graphic_levels()
1041 smu_data->smc_state_table.GraphicsDpmLevelCount = in fiji_populate_all_graphic_levels()
1231 smu_data->smc_state_table.MemoryLevel; in fiji_populate_all_memory_levels()
1256 smu_data->smc_state_table.MemoryDpmLevelCount = in fiji_populate_all_memory_levels()
1643 smu_data->smc_state_table.GraphicsBootLevel = level; in fiji_populate_smc_initailial_state()
1652 smu_data->smc_state_table.MemoryBootLevel = level; in fiji_populate_smc_initailial_state()
1697 smu_data->smc_state_table.ClockStretcherAmount = stretch_amount; in fiji_populate_clock_stretcher_data_table()
1701 smu_data->smc_state_table.Sclk_CKS_masterEn0_7 |= in fiji_populate_clock_stretcher_data_table()
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Dpolaris10_smumgr.c432 SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table); in polaris10_populate_bapm_parameters_in_dpm_table()
478 SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table); in polaris10_populate_zero_rpm_parameters()
836 smu_data->smc_state_table.LinkLevelCount = in polaris10_populate_smc_link_level()
894 const SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table); in polaris10_calculate_sclk_params()
1029 SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table); in polaris10_get_vddc_shared_railinfo()
1051 smu_data->smc_state_table.GraphicsLevel; in polaris10_populate_all_graphic_levels()
1065 polaris10_get_sclk_range_table(hwmgr, &(smu_data->smc_state_table)); in polaris10_populate_all_graphic_levels()
1071 &(smu_data->smc_state_table.GraphicsLevel[i])); in polaris10_populate_all_graphic_levels()
1081 smu_data->smc_state_table.GraphicsLevel[0].SclkSetting.SSc_En = 0; in polaris10_populate_all_graphic_levels()
1097 smu_data->smc_state_table.GraphicsDpmLevelCount = in polaris10_populate_all_graphic_levels()
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Dci_smumgr.c484 smu_data->smc_state_table.GraphicsLevel; in ci_populate_all_graphic_levels()
494 smu_data->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0; in ci_populate_all_graphic_levels()
496 smu_data->smc_state_table.GraphicsLevel[i].DisplayWatermark = in ci_populate_all_graphic_levels()
500 smu_data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1; in ci_populate_all_graphic_levels()
502 smu_data->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count; in ci_populate_all_graphic_levels()
721 SMU7_Discrete_DpmTable *dpm_table = &(smu_data->smc_state_table); in ci_populate_bapm_parameters_in_dpm_table()
1016 smu_data->smc_state_table.LinkLevelCount = in ci_populate_smc_link_level()
1312 SMU7_Discrete_MemoryLevel *levels = smu_data->smc_state_table.MemoryLevel; in ci_populate_all_memory_levels()
1321 &(smu_data->smc_state_table.MemoryLevel[i])); in ci_populate_all_memory_levels()
1326 smu_data->smc_state_table.MemoryLevel[0].EnabledForActivity = 1; in ci_populate_all_memory_levels()
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Dvegam_smumgr.c338 smu_data->smc_state_table.UvdBootLevel = 0; in vegam_update_uvd_smc_table()
340 smu_data->smc_state_table.UvdBootLevel = in vegam_update_uvd_smc_table()
349 mm_boot_level_value |= smu_data->smc_state_table.UvdBootLevel << 24; in vegam_update_uvd_smc_table()
359 (uint32_t)(1 << smu_data->smc_state_table.UvdBootLevel), in vegam_update_uvd_smc_table()
373 smu_data->smc_state_table.VceBootLevel = in vegam_update_vce_smc_table()
376 smu_data->smc_state_table.VceBootLevel = 0; in vegam_update_vce_smc_table()
385 mm_boot_level_value |= smu_data->smc_state_table.VceBootLevel << 16; in vegam_update_vce_smc_table()
392 (uint32_t)1 << smu_data->smc_state_table.VceBootLevel, in vegam_update_vce_smc_table()
591 smu_data->smc_state_table.LinkLevelCount = in vegam_populate_smc_link_level()
724 const SMU75_Discrete_DpmTable *table = &(smu_data->smc_state_table); in vegam_calculate_sclk_params()
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Diceland_smumgr.c787 smu_data->smc_state_table.LinkLevelCount = in iceland_populate_smc_link_level()
970 SMU71_Discrete_GraphicsLevel *levels = smu_data->smc_state_table.GraphicsLevel; in iceland_populate_all_graphic_levels()
983 &(smu_data->smc_state_table.GraphicsLevel[i])); in iceland_populate_all_graphic_levels()
989 smu_data->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0; in iceland_populate_all_graphic_levels()
993 smu_data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1; in iceland_populate_all_graphic_levels()
997 smu_data->smc_state_table.GraphicsLevel[dpm_table->sclk_table.count-1].DisplayWatermark = in iceland_populate_all_graphic_levels()
1000 smu_data->smc_state_table.GraphicsDpmLevelCount = in iceland_populate_all_graphic_levels()
1027 smu_data->smc_state_table.GraphicsLevel[i].pcieDpmLevel = highest_pcie_level_enabled; in iceland_populate_all_graphic_levels()
1031 smu_data->smc_state_table.GraphicsLevel[0].pcieDpmLevel = lowest_pcie_level_enabled; in iceland_populate_all_graphic_levels()
1034 smu_data->smc_state_table.GraphicsLevel[1].pcieDpmLevel = mid_pcie_level_enabled; in iceland_populate_all_graphic_levels()
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Dfiji_smumgr.h42 struct SMU73_Discrete_DpmTable smc_state_table; member
Dpolaris10_smumgr.h57 SMU74_Discrete_DpmTable smc_state_table; member
Diceland_smumgr.h62 struct SMU71_Discrete_DpmTable smc_state_table; member
Dvegam_smumgr.h66 SMU75_Discrete_DpmTable smc_state_table; member
Dci_smumgr.h68 struct SMU7_Discrete_DpmTable smc_state_table; member
Dtonga_smumgr.h66 struct SMU72_Discrete_DpmTable smc_state_table; member
/linux-6.1.9/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
Dvega10_hwmgr.c955 PPTable_t *pp_table = &(data->smc_state_table.pp_table); in vega10_setup_dpm_led_config()
1476 data->smc_state_table.pp_table.UlvOffsetVid = in vega10_populate_ulv_state()
1479 data->smc_state_table.pp_table.UlvSmnclkDid = in vega10_populate_ulv_state()
1481 data->smc_state_table.pp_table.UlvMp1clkDid = in vega10_populate_ulv_state()
1483 data->smc_state_table.pp_table.UlvGfxclkBypass = in vega10_populate_ulv_state()
1485 data->smc_state_table.pp_table.UlvPhaseSheddingPsi0 = in vega10_populate_ulv_state()
1487 data->smc_state_table.pp_table.UlvPhaseSheddingPsi1 = in vega10_populate_ulv_state()
1516 PPTable_t *pp_table = &(data->smc_state_table.pp_table); in vega10_override_pcie_parameters()
1563 PPTable_t *pp_table = &(data->smc_state_table.pp_table); in vega10_populate_smc_link_levels()
1725 PPTable_t *pp_table = &(data->smc_state_table.pp_table); in vega10_populate_all_graphic_levels()
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Dvega10_thermal.c510 PPTable_t *table = &(data->smc_state_table.pp_table); in vega10_thermal_setup_fan_table()
555 (uint8_t *)(&(data->smc_state_table.pp_table)), in vega10_thermal_setup_fan_table()
566 PPTable_t *table = &(data->smc_state_table.pp_table); in vega10_enable_mgpu_fan_boost()
580 (uint8_t *)(&(data->smc_state_table.pp_table)), in vega10_enable_mgpu_fan_boost()
Dvega12_thermal.c254 PPTable_t *table = &(data->smc_state_table.pp_table); in vega12_thermal_setup_fan_table()
Dvega20_thermal.c325 PPTable_t *table = &(data->smc_state_table.pp_table); in vega20_thermal_setup_fan_table()
Dvega20_hwmgr.c785 PPTable_t *pp_table = &(data->smc_state_table.pp_table); in vega20_init_smc_table()
836 PPTable_t *pp_table = &(data->smc_state_table.pp_table); in vega20_override_pcie_parameters()
1043 PPTable_t *pp_table = &(data->smc_state_table.pp_table); in vega20_od8_set_feature_capabilities()
1244 OverDriveTable_t *od_table = &(data->smc_state_table.overdrive_table); in vega20_od8_initialize_default_settings()
1345 od_table->FanMinimumPwm * data->smc_state_table.pp_table.FanMaximumRpm / 100; in vega20_od8_initialize_default_settings()
2940 Watermarks_t *table = &(data->smc_state_table.water_marks_table); in vega20_set_watermarks_for_clocks_ranges()
2963 &(data->smc_state_table.overdrive_table); in vega20_odn_edit_dpm_table()
3361 &(data->smc_state_table.overdrive_table); in vega20_print_clock_levels()
3362 PPTable_t *pptable = &(data->smc_state_table.pp_table); in vega20_print_clock_levels()
3644 Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table); in vega20_display_configuration_changed_task()
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Dvega10_hwmgr.h381 struct vega10_smc_state_table smc_state_table; member
Dvega12_hwmgr.h393 struct vega12_smc_state_table smc_state_table; member
Dvega20_hwmgr.h522 struct vega20_smc_state_table smc_state_table; member
Dvega12_hwmgr.c491 PPTable_t *pp_table = &(data->smc_state_table.pp_table); in vega12_override_pcie_parameters()
816 PPTable_t *pp_table = &(data->smc_state_table.pp_table); in vega12_init_smc_table()
1980 Watermarks_t *table = &(data->smc_state_table.water_marks_table); in vega12_set_watermarks_for_clocks_ranges()
2532 Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table); in vega12_display_configuration_changed_task()
2747 PPTable_t *pp_table = &(data->smc_state_table.pp_table); in vega12_get_thermal_temperature_range()
Dvega10_powertune.c1269 PPTable_t *table = &(data->smc_state_table.pp_table); in vega10_initialize_power_tune_defaults()
Dsmu7_hwmgr.c5272 SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table); in smu7_set_watermarks_for_clocks_ranges()
/linux-6.1.9/drivers/gpu/drm/radeon/
Dci_dpm.c410 SMU7_Discrete_DpmTable *dpm_table = &pi->smc_state_table; in ci_populate_bapm_parameters_in_dpm_table()
1280 SMU7_Discrete_DpmTable *table = &pi->smc_state_table; in ci_init_fps_limits()
2557 pi->smc_state_table.GraphicsBootLevel = level; in ci_populate_smc_initial_state()
2565 pi->smc_state_table.MemoryBootLevel = level; in ci_populate_smc_initial_state()
2604 pi->smc_state_table.LinkLevelCount = (u8)dpm_table->pcie_speed_table.count; in ci_populate_smc_link_level()
3245 SMU7_Discrete_GraphicsLevel *levels = pi->smc_state_table.GraphicsLevel; in ci_populate_all_graphic_levels()
3254 &pi->smc_state_table.GraphicsLevel[i]); in ci_populate_all_graphic_levels()
3258 pi->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0; in ci_populate_all_graphic_levels()
3260 pi->smc_state_table.GraphicsLevel[i].DisplayWatermark = in ci_populate_all_graphic_levels()
3263 pi->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1; in ci_populate_all_graphic_levels()
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Dci_dpm.h224 SMU7_Discrete_DpmTable smc_state_table; member