Home
last modified time | relevance | path

Searched refs:se_num (Results 1 – 21 of 21) sorted by relevance

/linux-6.1.9/drivers/gpu/drm/amd/amdgpu/
Dsoc21.c218 static uint32_t soc21_read_indexed_register(struct amdgpu_device *adev, u32 se_num, in soc21_read_indexed_register() argument
224 if (se_num != 0xffffffff || sh_num != 0xffffffff) in soc21_read_indexed_register()
225 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); in soc21_read_indexed_register()
229 if (se_num != 0xffffffff || sh_num != 0xffffffff) in soc21_read_indexed_register()
236 bool indexed, u32 se_num, in soc21_get_register_value() argument
240 return soc21_read_indexed_register(adev, se_num, sh_num, reg_offset); in soc21_get_register_value()
248 static int soc21_read_register(struct amdgpu_device *adev, u32 se_num, in soc21_read_register() argument
264 se_num, sh_num, reg_offset); in soc21_read_register()
Dnv.c357 static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num, in nv_read_indexed_register() argument
363 if (se_num != 0xffffffff || sh_num != 0xffffffff) in nv_read_indexed_register()
364 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); in nv_read_indexed_register()
368 if (se_num != 0xffffffff || sh_num != 0xffffffff) in nv_read_indexed_register()
375 bool indexed, u32 se_num, in nv_get_register_value() argument
379 return nv_read_indexed_register(adev, se_num, sh_num, reg_offset); in nv_get_register_value()
387 static int nv_read_register(struct amdgpu_device *adev, u32 se_num, in nv_read_register() argument
403 se_num, sh_num, reg_offset); in nv_read_register()
Dgfx_v9_0.h29 void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num,
Dsoc15.c401 static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num, in soc15_read_indexed_register() argument
407 if (se_num != 0xffffffff || sh_num != 0xffffffff) in soc15_read_indexed_register()
408 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); in soc15_read_indexed_register()
412 if (se_num != 0xffffffff || sh_num != 0xffffffff) in soc15_read_indexed_register()
419 bool indexed, u32 se_num, in soc15_get_register_value() argument
423 return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset); in soc15_get_register_value()
433 static int soc15_read_register(struct amdgpu_device *adev, u32 se_num, in soc15_read_register() argument
449 se_num, sh_num, reg_offset); in soc15_read_register()
Dcik.c1123 bool indexed, u32 se_num, in cik_get_register_value() argument
1128 unsigned se_idx = (se_num == 0xffffffff) ? 0 : se_num; in cik_get_register_value()
1143 if (se_num != 0xffffffff || sh_num != 0xffffffff) in cik_get_register_value()
1144 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); in cik_get_register_value()
1148 if (se_num != 0xffffffff || sh_num != 0xffffffff) in cik_get_register_value()
1218 static int cik_read_register(struct amdgpu_device *adev, u32 se_num, in cik_read_register() argument
1230 *value = cik_get_register_value(adev, indexed, se_num, sh_num, in cik_read_register()
Dgfx_v9_4.c93 static void gfx_v9_4_select_se_sh(struct amdgpu_device *adev, u32 se_num, in gfx_v9_4_select_se_sh() argument
105 if (se_num == 0xffffffff) in gfx_v9_4_select_se_sh()
109 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); in gfx_v9_4_select_se_sh()
883 for (j = 0; j < gfx_v9_4_edc_counter_regs[i].se_num; j++) { in gfx_v9_4_query_ras_error_count()
917 for (j = 0; j < gfx_v9_4_edc_counter_regs[i].se_num; j++) { in gfx_v9_4_reset_ras_error_count()
1009 for (i = 0; i < gfx_v9_4_ea_err_status_regs.se_num; i++) { in gfx_v9_4_query_ras_error_status()
Dvi.c748 bool indexed, u32 se_num, in vi_get_register_value() argument
753 unsigned se_idx = (se_num == 0xffffffff) ? 0 : se_num; in vi_get_register_value()
768 if (se_num != 0xffffffff || sh_num != 0xffffffff) in vi_get_register_value()
769 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); in vi_get_register_value()
773 if (se_num != 0xffffffff || sh_num != 0xffffffff) in vi_get_register_value()
843 static int vi_read_register(struct amdgpu_device *adev, u32 se_num, in vi_read_register() argument
855 *value = vi_get_register_value(adev, indexed, se_num, sh_num, in vi_read_register()
Dsoc15.h65 uint32_t se_num; member
Dsi.c1165 bool indexed, u32 se_num, in si_get_register_value() argument
1170 unsigned se_idx = (se_num == 0xffffffff) ? 0 : se_num; in si_get_register_value()
1183 if (se_num != 0xffffffff || sh_num != 0xffffffff) in si_get_register_value()
1184 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); in si_get_register_value()
1188 if (se_num != 0xffffffff || sh_num != 0xffffffff) in si_get_register_value()
1239 static int si_read_register(struct amdgpu_device *adev, u32 se_num, in si_read_register() argument
1251 *value = si_get_register_value(adev, indexed, se_num, sh_num, in si_read_register()
Damdgpu_kms.c723 unsigned se_num = (info->read_mmr_reg.instance >> in amdgpu_info_ioctl() local
732 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK) in amdgpu_info_ioctl()
733 se_num = 0xffffffff; in amdgpu_info_ioctl()
734 else if (se_num >= AMDGPU_GFX_MAX_SE) in amdgpu_info_ioctl()
751 if (amdgpu_asic_read_register(adev, se_num, sh_num, in amdgpu_info_ioctl()
Dgfx_v9_4_2.c846 static void gfx_v9_4_2_select_se_sh(struct amdgpu_device *adev, u32 se_num, in gfx_v9_4_2_select_se_sh() argument
858 if (se_num == 0xffffffff) in gfx_v9_4_2_select_se_sh()
862 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); in gfx_v9_4_2_select_se_sh()
1502 for (j = 0; j < gfx_v9_4_2_edc_counter_regs[i].se_num; j++) { in gfx_v9_4_2_query_sram_edc_count()
1679 for (i = 0; i < gfx_v9_4_2_ea_err_status_regs.se_num; i++) { in gfx_v9_4_2_reset_ea_err_status()
1731 for (i = 0; i < gfx_v9_4_2_ea_err_status_regs.se_num; i++) { in gfx_v9_4_2_query_ea_err_status()
Damdgpu_gfx.h217 void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num,
Dgfx_v6_0.c1301 static void gfx_v6_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, in gfx_v6_0_select_se_sh() argument
1311 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) in gfx_v6_0_select_se_sh()
1314 else if (se_num == 0xffffffff) in gfx_v6_0_select_se_sh()
1319 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT); in gfx_v6_0_select_se_sh()
1322 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT); in gfx_v6_0_select_se_sh()
Dgfx_v7_0.c1589 u32 se_num, u32 sh_num, u32 instance) in gfx_v7_0_select_se_sh() argument
1598 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) in gfx_v7_0_select_se_sh()
1601 else if (se_num == 0xffffffff) in gfx_v7_0_select_se_sh()
1606 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT); in gfx_v7_0_select_se_sh()
1609 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT); in gfx_v7_0_select_se_sh()
Damdgpu.h555 int (*read_register)(struct amdgpu_device *adev, u32 se_num,
Dgfx_v9_0.c2277 void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, in gfx_v9_0_select_se_sh() argument
2287 if (se_num == 0xffffffff) in gfx_v9_0_select_se_sh()
2290 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); in gfx_v9_0_select_se_sh()
6483 for (j = 0; j < gfx_v9_0_edc_counter_regs[i].se_num; j++) { in gfx_v9_0_reset_ras_error_count()
6545 for (j = 0; j < gfx_v9_0_edc_counter_regs[i].se_num; j++) { in gfx_v9_0_query_ras_error_count()
Dgfx_v11_0.c113 static void gfx_v11_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
1494 static void gfx_v11_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, in gfx_v11_0_select_se_sh() argument
1506 if (se_num == 0xffffffff) in gfx_v11_0_select_se_sh()
1510 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); in gfx_v11_0_select_se_sh()
Dgfx_v8_0.c3424 u32 se_num, u32 sh_num, u32 instance) in gfx_v8_0_select_se_sh() argument
3433 if (se_num == 0xffffffff) in gfx_v8_0_select_se_sh()
3436 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); in gfx_v8_0_select_se_sh()
Dgfx_v10_0.c3492 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
4793 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, in gfx_v10_0_select_se_sh() argument
4805 if (se_num == 0xffffffff) in gfx_v10_0_select_se_sh()
4809 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); in gfx_v10_0_select_se_sh()
/linux-6.1.9/drivers/gpu/drm/radeon/
Dsi.c2947 u32 se_num, u32 sh_num) in si_select_se_sh() argument
2951 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) in si_select_se_sh()
2953 else if (se_num == 0xffffffff) in si_select_se_sh()
2956 data |= SH_BROADCAST_WRITES | SE_INDEX(se_num); in si_select_se_sh()
2958 data |= SH_INDEX(sh_num) | SE_INDEX(se_num); in si_select_se_sh()
2992 u32 se_num, u32 sh_per_se, in si_setup_spi() argument
2998 for (i = 0; i < se_num; i++) { in si_setup_spi()
3039 u32 se_num, u32 sh_per_se, in si_setup_rb() argument
3047 for (i = 0; i < se_num; i++) { in si_setup_rb()
3057 for (i = 0; i < max_rb_num_per_se * se_num; i++) { in si_setup_rb()
[all …]
Dcik.c3027 u32 se_num, u32 sh_num) in cik_select_se_sh() argument
3031 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) in cik_select_se_sh()
3033 else if (se_num == 0xffffffff) in cik_select_se_sh()
3036 data |= SH_BROADCAST_WRITES | SE_INDEX(se_num); in cik_select_se_sh()
3038 data |= SH_INDEX(sh_num) | SE_INDEX(se_num); in cik_select_se_sh()
3102 u32 se_num, u32 sh_per_se, in cik_setup_rb() argument
3110 for (i = 0; i < se_num; i++) { in cik_setup_rb()
3123 for (i = 0; i < max_rb_num_per_se * se_num; i++) { in cik_setup_rb()
3131 for (i = 0; i < se_num; i++) { in cik_setup_rb()