Searched refs:sdma_rlc_reg_offset (Results 1 – 7 of 7) sorted by relevance
/linux-6.1.9/drivers/gpu/drm/amd/amdgpu/ |
D | amdgpu_amdkfd_arcturus.c | 70 uint32_t sdma_rlc_reg_offset; in get_sdma_rlc_reg_offset() local 112 sdma_rlc_reg_offset = sdma_engine_reg_base in get_sdma_rlc_reg_offset() 116 queue_id, sdma_rlc_reg_offset); in get_sdma_rlc_reg_offset() 118 return sdma_rlc_reg_offset; in get_sdma_rlc_reg_offset() 125 uint32_t sdma_rlc_reg_offset; in kgd_arcturus_hqd_sdma_load() local 132 sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, m->sdma_engine_id, in kgd_arcturus_hqd_sdma_load() 135 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, in kgd_arcturus_hqd_sdma_load() 140 data = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS); in kgd_arcturus_hqd_sdma_load() 150 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL_OFFSET, in kgd_arcturus_hqd_sdma_load() 155 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, data); in kgd_arcturus_hqd_sdma_load() [all …]
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D | amdgpu_amdkfd_gfx_v11.c | 128 uint32_t sdma_rlc_reg_offset; in get_sdma_rlc_reg_offset() local 143 sdma_rlc_reg_offset = sdma_engine_reg_base in get_sdma_rlc_reg_offset() 147 queue_id, sdma_rlc_reg_offset); in get_sdma_rlc_reg_offset() 149 return sdma_rlc_reg_offset; in get_sdma_rlc_reg_offset() 346 uint32_t sdma_rlc_reg_offset; in hqd_sdma_load_v11() local 353 sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, m->sdma_engine_id, in hqd_sdma_load_v11() 356 WREG32(sdma_rlc_reg_offset + regSDMA0_QUEUE0_RB_CNTL, in hqd_sdma_load_v11() 361 data = RREG32(sdma_rlc_reg_offset + regSDMA0_QUEUE0_CONTEXT_STATUS); in hqd_sdma_load_v11() 371 WREG32(sdma_rlc_reg_offset + regSDMA0_QUEUE0_DOORBELL_OFFSET, in hqd_sdma_load_v11() 376 WREG32(sdma_rlc_reg_offset + regSDMA0_QUEUE0_DOORBELL, data); in hqd_sdma_load_v11() [all …]
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D | amdgpu_amdkfd_gfx_v9.c | 183 uint32_t sdma_rlc_reg_offset; in get_sdma_rlc_reg_offset() local 201 sdma_rlc_reg_offset = sdma_engine_reg_base in get_sdma_rlc_reg_offset() 205 queue_id, sdma_rlc_reg_offset); in get_sdma_rlc_reg_offset() 207 return sdma_rlc_reg_offset; in get_sdma_rlc_reg_offset() 386 uint32_t sdma_rlc_reg_offset; in kgd_hqd_sdma_load() local 393 sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, m->sdma_engine_id, in kgd_hqd_sdma_load() 396 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, in kgd_hqd_sdma_load() 401 data = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS); in kgd_hqd_sdma_load() 411 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL_OFFSET, in kgd_hqd_sdma_load() 416 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, data); in kgd_hqd_sdma_load() [all …]
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D | amdgpu_amdkfd_gfx_v10.c | 374 uint32_t sdma_rlc_reg_offset; in kgd_hqd_sdma_load() local 381 sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, m->sdma_engine_id, in kgd_hqd_sdma_load() 384 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, in kgd_hqd_sdma_load() 389 data = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS); in kgd_hqd_sdma_load() 399 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL_OFFSET, in kgd_hqd_sdma_load() 404 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, data); in kgd_hqd_sdma_load() 405 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR, in kgd_hqd_sdma_load() 407 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_HI, in kgd_hqd_sdma_load() 410 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 1); in kgd_hqd_sdma_load() 412 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR, in kgd_hqd_sdma_load() [all …]
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D | amdgpu_amdkfd_gfx_v10_3.c | 132 uint32_t sdma_rlc_reg_offset; in get_sdma_rlc_reg_offset() local 158 sdma_rlc_reg_offset = sdma_engine_reg_base in get_sdma_rlc_reg_offset() 162 queue_id, sdma_rlc_reg_offset); in get_sdma_rlc_reg_offset() 164 return sdma_rlc_reg_offset; in get_sdma_rlc_reg_offset() 361 uint32_t sdma_rlc_reg_offset; in hqd_sdma_load_v10_3() local 368 sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, m->sdma_engine_id, in hqd_sdma_load_v10_3() 371 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, in hqd_sdma_load_v10_3() 376 data = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS); in hqd_sdma_load_v10_3() 386 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL_OFFSET, in hqd_sdma_load_v10_3() 391 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, data); in hqd_sdma_load_v10_3() [all …]
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D | amdgpu_amdkfd_gfx_v7.c | 243 uint32_t sdma_rlc_reg_offset; in kgd_hqd_sdma_load() local 247 sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(m); in kgd_hqd_sdma_load() 249 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, in kgd_hqd_sdma_load() 254 data = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS); in kgd_hqd_sdma_load() 266 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, data); in kgd_hqd_sdma_load() 267 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR, in kgd_hqd_sdma_load() 271 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR, data); in kgd_hqd_sdma_load() 273 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR, in kgd_hqd_sdma_load() 276 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_VIRTUAL_ADDR, in kgd_hqd_sdma_load() 278 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE, m->sdma_rlc_rb_base); in kgd_hqd_sdma_load() [all …]
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D | amdgpu_amdkfd_gfx_v8.c | 267 uint32_t sdma_rlc_reg_offset; in kgd_hqd_sdma_load() local 271 sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(m); in kgd_hqd_sdma_load() 272 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, in kgd_hqd_sdma_load() 277 data = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS); in kgd_hqd_sdma_load() 289 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, data); in kgd_hqd_sdma_load() 290 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR, in kgd_hqd_sdma_load() 294 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR, data); in kgd_hqd_sdma_load() 296 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR, in kgd_hqd_sdma_load() 299 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_VIRTUAL_ADDR, in kgd_hqd_sdma_load() 301 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE, m->sdmax_rlcx_rb_base); in kgd_hqd_sdma_load() [all …]
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