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Searched refs:sclk_table (Results 1 – 15 of 15) sorted by relevance

/linux-6.1.9/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
Dsmu7_hwmgr.c747 &data->dpm_table.sclk_table, in smu7_reset_dpm_tables()
805 data->dpm_table.sclk_table.count = 0; in smu7_setup_dpm_tables_v0()
808 if (i == 0 || data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count-1].value != in smu7_setup_dpm_tables_v0()
810 data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value = in smu7_setup_dpm_tables_v0()
812 …data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled = (i == 0) ? 1 : 0; in smu7_setup_dpm_tables_v0()
813 data->dpm_table.sclk_table.count++; in smu7_setup_dpm_tables_v0()
899 data->dpm_table.sclk_table.count = 0; in smu7_setup_dpm_tables_v1()
901 if (i == 0 || data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count - 1].value != in smu7_setup_dpm_tables_v1()
904 data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value = in smu7_setup_dpm_tables_v1()
907 data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled = in smu7_setup_dpm_tables_v1()
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Dprocess_pptables_v1_0.c407 phm_ppt_v1_clock_voltage_dependency_table *sclk_table; in get_sclk_voltage_dependency_table() local
418 sclk_table = kzalloc(struct_size(sclk_table, entries, tonga_table->ucNumEntries), in get_sclk_voltage_dependency_table()
420 if (!sclk_table) in get_sclk_voltage_dependency_table()
423 sclk_table->count = (uint32_t)tonga_table->ucNumEntries; in get_sclk_voltage_dependency_table()
431 entries, sclk_table, i); in get_sclk_voltage_dependency_table()
447 sclk_table = kzalloc(struct_size(sclk_table, entries, polaris_table->ucNumEntries), in get_sclk_voltage_dependency_table()
449 if (!sclk_table) in get_sclk_voltage_dependency_table()
452 sclk_table->count = (uint32_t)polaris_table->ucNumEntries; in get_sclk_voltage_dependency_table()
460 entries, sclk_table, i); in get_sclk_voltage_dependency_table()
470 *pp_tonga_sclk_dep_table = sclk_table; in get_sclk_voltage_dependency_table()
Dsmu7_hwmgr.h104 struct smu7_single_dpm_table sclk_table; member
Dvega10_hwmgr.c3395 struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table); in vega10_find_dpm_states_clocks_in_dpm_table() local
3403 for (i = 0; i < sclk_table->count; i++) { in vega10_find_dpm_states_clocks_in_dpm_table()
3404 if (sclk == sclk_table->dpm_levels[i].value) in vega10_find_dpm_states_clocks_in_dpm_table()
3408 if (i >= sclk_table->count) { in vega10_find_dpm_states_clocks_in_dpm_table()
3409 if (sclk > sclk_table->dpm_levels[i-1].value) { in vega10_find_dpm_states_clocks_in_dpm_table()
3411 sclk_table->dpm_levels[i-1].value = sclk; in vega10_find_dpm_states_clocks_in_dpm_table()
4632 struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table); in vega10_emit_clock_levels() local
4656 count = sclk_table->count; in vega10_emit_clock_levels()
4659 i, sclk_table->dpm_levels[i].value / 100, in vega10_emit_clock_levels()
4778 struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table); in vega10_print_clock_levels() local
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Dsmu8_hwmgr.c1548 struct phm_clock_voltage_dependency_table *sclk_table = in smu8_print_clock_levels() local
1561 for (i = 0; i < sclk_table->count; i++) in smu8_print_clock_levels()
1563 i, sclk_table->entries[i].clk / 100, in smu8_print_clock_levels()
Dvega12_hwmgr.c2670 struct vega12_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table);
2673 int value = sclk_table->dpm_levels[sclk_table->count - 1].value;
Dvega20_hwmgr.c1470 struct vega20_single_dpm_table *sclk_table = in vega20_get_sclk_od() local
1474 int value = sclk_table->dpm_levels[sclk_table->count - 1].value; in vega20_get_sclk_od()
/linux-6.1.9/drivers/gpu/drm/amd/pm/powerplay/smumgr/
Dvegam_smumgr.c889 for (i = 0; i < dpm_table->sclk_table.count; i++) { in vegam_populate_all_graphic_levels()
892 dpm_table->sclk_table.dpm_levels[i].value, in vegam_populate_all_graphic_levels()
910 (uint8_t)dpm_table->sclk_table.count; in vegam_populate_all_graphic_levels()
912 phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table); in vegam_populate_all_graphic_levels()
914 for (i = 0; i < dpm_table->sclk_table.count; i++) in vegam_populate_all_graphic_levels()
923 for (i = 0; i < dpm_table->sclk_table.count; i++) in vegam_populate_all_graphic_levels()
948 for (i = 2; i < dpm_table->sclk_table.count; i++) in vegam_populate_all_graphic_levels()
1288 for (i = 0; i < hw_data->dpm_table.sclk_table.count; i++) { in vegam_program_memory_timing_parameters()
1291 hw_data->dpm_table.sclk_table.dpm_levels[i].value, in vegam_program_memory_timing_parameters()
1375 result = phm_find_boot_level(&(data->dpm_table.sclk_table), in vegam_populate_smc_boot_level()
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Dpolaris10_smumgr.c1067 for (i = 0; i < dpm_table->sclk_table.count; i++) { in polaris10_populate_all_graphic_levels()
1070 dpm_table->sclk_table.dpm_levels[i].value, in polaris10_populate_all_graphic_levels()
1084 dpm_table->sclk_table.dpm_levels[0].value, in polaris10_populate_all_graphic_levels()
1091 dividers.real_clock < dpm_table->sclk_table.dpm_levels[0].value ? in polaris10_populate_all_graphic_levels()
1098 (uint8_t)dpm_table->sclk_table.count; in polaris10_populate_all_graphic_levels()
1100 phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table); in polaris10_populate_all_graphic_levels()
1111 for (i = 0; i < dpm_table->sclk_table.count; i++) in polaris10_populate_all_graphic_levels()
1136 for (i = 2; i < dpm_table->sclk_table.count; i++) in polaris10_populate_all_graphic_levels()
1498 for (i = 0; i < hw_data->dpm_table.sclk_table.count; i++) { in polaris10_program_memory_timing_parameters()
1501 hw_data->dpm_table.sclk_table.dpm_levels[i].value, in polaris10_program_memory_timing_parameters()
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Dfiji_smumgr.c1022 for (i = 0; i < dpm_table->sclk_table.count; i++) { in fiji_populate_all_graphic_levels()
1024 dpm_table->sclk_table.dpm_levels[i].value, in fiji_populate_all_graphic_levels()
1038 levels[dpm_table->sclk_table.count - 1].DisplayWatermark = in fiji_populate_all_graphic_levels()
1042 (uint8_t)dpm_table->sclk_table.count; in fiji_populate_all_graphic_levels()
1044 phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table); in fiji_populate_all_graphic_levels()
1051 for (i = 0; i < dpm_table->sclk_table.count; i++) in fiji_populate_all_graphic_levels()
1076 for (i = 2; i < dpm_table->sclk_table.count; i++) in fiji_populate_all_graphic_levels()
1316 data->dpm_table.sclk_table.dpm_levels[0].value; in fiji_populate_smc_acpi_level()
1532 for (i = 0; i < data->dpm_table.sclk_table.count; i++) { in fiji_program_memory_timing_parameters()
1535 data->dpm_table.sclk_table.dpm_levels[i].value, in fiji_program_memory_timing_parameters()
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Dtonga_smumgr.c710 for (i = 0; i < dpm_table->sclk_table.count; i++) { in tonga_populate_all_graphic_levels()
712 dpm_table->sclk_table.dpm_levels[i].value, in tonga_populate_all_graphic_levels()
726 if (dpm_table->sclk_table.count > 1) in tonga_populate_all_graphic_levels()
727 smu_data->smc_state_table.GraphicsLevel[dpm_table->sclk_table.count-1].DisplayWatermark = in tonga_populate_all_graphic_levels()
731 (uint8_t)dpm_table->sclk_table.count; in tonga_populate_all_graphic_levels()
733 phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table); in tonga_populate_all_graphic_levels()
740 for (i = 0; i < dpm_table->sclk_table.count; i++) { in tonga_populate_all_graphic_levels()
770 for (i = 2; i < dpm_table->sclk_table.count; i++) in tonga_populate_all_graphic_levels()
1497 for (i = 0; i < data->dpm_table.sclk_table.count; i++) { in tonga_program_memory_timing_parameters()
1500 (hwmgr, data->dpm_table.sclk_table.dpm_levels[i].value, in tonga_program_memory_timing_parameters()
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Diceland_smumgr.c980 for (i = 0; i < dpm_table->sclk_table.count; i++) { in iceland_populate_all_graphic_levels()
982 dpm_table->sclk_table.dpm_levels[i].value, in iceland_populate_all_graphic_levels()
996 if (dpm_table->sclk_table.count > 1) in iceland_populate_all_graphic_levels()
997 smu_data->smc_state_table.GraphicsLevel[dpm_table->sclk_table.count-1].DisplayWatermark = in iceland_populate_all_graphic_levels()
1001 (uint8_t)dpm_table->sclk_table.count; in iceland_populate_all_graphic_levels()
1003 phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table); in iceland_populate_all_graphic_levels()
1026 for (i = 2; i < dpm_table->sclk_table.count; i++) { in iceland_populate_all_graphic_levels()
1621 for (i = 0; i < data->dpm_table.sclk_table.count; i++) { in iceland_program_memory_timing_parameters()
1624 (hwmgr, data->dpm_table.sclk_table.dpm_levels[i].value, in iceland_program_memory_timing_parameters()
1657 result = phm_find_boot_level(&(data->dpm_table.sclk_table), in iceland_populate_smc_boot_level()
Dci_smumgr.c487 for (i = 0; i < dpm_table->sclk_table.count; i++) { in ci_populate_all_graphic_levels()
489 dpm_table->sclk_table.dpm_levels[i].value, in ci_populate_all_graphic_levels()
495 if (i == (dpm_table->sclk_table.count - 1)) in ci_populate_all_graphic_levels()
502 smu_data->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count; in ci_populate_all_graphic_levels()
504 phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table); in ci_populate_all_graphic_levels()
1661 for (i = 0; i < data->dpm_table.sclk_table.count; i++) { in ci_program_memory_timing_parameters()
1664 (hwmgr, data->dpm_table.sclk_table.dpm_levels[i].value, in ci_program_memory_timing_parameters()
1697 result = phm_find_boot_level(&(data->dpm_table.sclk_table), in ci_populate_smc_boot_level()
/linux-6.1.9/drivers/gpu/drm/radeon/
Dci_dpm.c2516 for (i = 0; i < pi->dpm_table.sclk_table.count; i++) { in ci_do_program_memory_timing_parameters()
2519 pi->dpm_table.sclk_table.dpm_levels[i].value, in ci_do_program_memory_timing_parameters()
3250 for (i = 0; i < dpm_table->sclk_table.count; i++) { in ci_populate_all_graphic_levels()
3252 dpm_table->sclk_table.dpm_levels[i].value, in ci_populate_all_graphic_levels()
3259 if (i == (dpm_table->sclk_table.count - 1)) in ci_populate_all_graphic_levels()
3265 pi->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count; in ci_populate_all_graphic_levels()
3267 ci_get_dpm_level_enable_mask_value(&dpm_table->sclk_table); in ci_populate_all_graphic_levels()
3425 &pi->dpm_table.sclk_table, in ci_setup_default_dpm_tables()
3440 pi->dpm_table.sclk_table.count = 0; in ci_setup_default_dpm_tables()
3443 (pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count-1].value != in ci_setup_default_dpm_tables()
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Dci_dpm.h69 struct ci_single_dpm_table sclk_table; member