Searched refs:sclk_post_div_slow (Results 1 – 2 of 2) sorted by relevance
707 u32 sclk_post_div_slow : 4; member
1224 w100_pwr_state.sclk_cntl.f.sclk_post_div_slow = 0x0; /* Pslow = 1 */ in w100_pwm_setup()1300 w100_pwr_state.sclk_cntl.f.sclk_post_div_slow = mode->sysclk_divider; in w100_init_clocks()