Searched refs:rlc_hdr (Results 1 – 8 of 8) sorted by relevance
279 const struct rlc_firmware_header_v2_0 *rlc_hdr; in amdgpu_gfx_rlc_init_microcode_v2_0() local284 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; in amdgpu_gfx_rlc_init_microcode_v2_0()286 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version); in amdgpu_gfx_rlc_init_microcode_v2_0()287 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version); in amdgpu_gfx_rlc_init_microcode_v2_0()289 le32_to_cpu(rlc_hdr->save_and_restore_offset); in amdgpu_gfx_rlc_init_microcode_v2_0()291 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset); in amdgpu_gfx_rlc_init_microcode_v2_0()293 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations); in amdgpu_gfx_rlc_init_microcode_v2_0()295 le32_to_cpu(rlc_hdr->reg_restore_list_size); in amdgpu_gfx_rlc_init_microcode_v2_0()297 le32_to_cpu(rlc_hdr->reg_list_format_start); in amdgpu_gfx_rlc_init_microcode_v2_0()299 le32_to_cpu(rlc_hdr->reg_list_format_separate_start); in amdgpu_gfx_rlc_init_microcode_v2_0()[all …]
151 const struct rlc_firmware_header_v1_0 *rlc_hdr = in amdgpu_ucode_print_rlc_hdr() local155 le32_to_cpu(rlc_hdr->ucode_feature_version)); in amdgpu_ucode_print_rlc_hdr()157 le32_to_cpu(rlc_hdr->save_and_restore_offset)); in amdgpu_ucode_print_rlc_hdr()159 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset)); in amdgpu_ucode_print_rlc_hdr()161 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations)); in amdgpu_ucode_print_rlc_hdr()163 le32_to_cpu(rlc_hdr->master_pkt_description_offset)); in amdgpu_ucode_print_rlc_hdr()165 const struct rlc_firmware_header_v2_0 *rlc_hdr = in amdgpu_ucode_print_rlc_hdr() local168 container_of(rlc_hdr, struct rlc_firmware_header_v2_1, v2_0); in amdgpu_ucode_print_rlc_hdr()180 le32_to_cpu(rlc_hdr->ucode_feature_version)); in amdgpu_ucode_print_rlc_hdr()181 DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(rlc_hdr->jt_offset)); in amdgpu_ucode_print_rlc_hdr()[all …]
953 const struct rlc_firmware_header_v2_0 *rlc_hdr; in gfx_v8_0_init_microcode() local1067 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; in gfx_v8_0_init_microcode()1068 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version); in gfx_v8_0_init_microcode()1069 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version); in gfx_v8_0_init_microcode()1072 le32_to_cpu(rlc_hdr->save_and_restore_offset); in gfx_v8_0_init_microcode()1074 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset); in gfx_v8_0_init_microcode()1076 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations); in gfx_v8_0_init_microcode()1078 le32_to_cpu(rlc_hdr->reg_restore_list_size); in gfx_v8_0_init_microcode()1080 le32_to_cpu(rlc_hdr->reg_list_format_start); in gfx_v8_0_init_microcode()1082 le32_to_cpu(rlc_hdr->reg_list_format_separate_start); in gfx_v8_0_init_microcode()[all …]
451 const struct rlc_firmware_header_v2_0 *rlc_hdr; in gfx_v11_0_init_microcode() local502 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; in gfx_v11_0_init_microcode()503 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); in gfx_v11_0_init_microcode()504 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); in gfx_v11_0_init_microcode()1063 const struct rlc_firmware_header_v2_0 *rlc_hdr; in gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode() local1154 rlc_hdr = (const struct rlc_firmware_header_v2_0 *) in gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode()1157 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes)); in gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode()1158 fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes); in gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode()1162 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); in gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode()1163 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); in gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode()
317 const struct rlc_firmware_header_v1_0 *rlc_hdr; in gfx_v6_0_init_microcode() local378 rlc_hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data; in gfx_v6_0_init_microcode()379 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version); in gfx_v6_0_init_microcode()380 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version); in gfx_v6_0_init_microcode()
3981 const struct rlc_firmware_header_v2_0 *rlc_hdr; in gfx_v10_0_init_microcode() local4072 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; in gfx_v10_0_init_microcode()4073 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); in gfx_v10_0_init_microcode()4074 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); in gfx_v10_0_init_microcode()5407 const struct rlc_firmware_header_v2_0 *rlc_hdr; in gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode() local5440 rlc_hdr = (const struct rlc_firmware_header_v2_0 *) in gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode()5443 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes)); in gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode()5444 fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes); in gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode()
1303 const struct rlc_firmware_header_v2_0 *rlc_hdr; in gfx_v9_0_init_rlc_microcode() local1334 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; in gfx_v9_0_init_rlc_microcode()1336 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); in gfx_v9_0_init_rlc_microcode()1337 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); in gfx_v9_0_init_rlc_microcode()
115 const struct rlc_firmware_header_v1_0 *rlc_hdr = in radeon_ucode_print_rlc_hdr() local119 le32_to_cpu(rlc_hdr->ucode_feature_version)); in radeon_ucode_print_rlc_hdr()121 le32_to_cpu(rlc_hdr->save_and_restore_offset)); in radeon_ucode_print_rlc_hdr()123 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset)); in radeon_ucode_print_rlc_hdr()125 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations)); in radeon_ucode_print_rlc_hdr()127 le32_to_cpu(rlc_hdr->master_pkt_description_offset)); in radeon_ucode_print_rlc_hdr()