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Searched refs:res_pool (Results 1 – 25 of 75) sorted by relevance

123

/linux-6.1.9/drivers/bus/fsl-mc/
Dfsl-mc-allocator.c37 struct fsl_mc_resource_pool *res_pool; in fsl_mc_resource_pool_add_device() local
49 res_pool = &mc_bus->resource_pools[pool_type]; in fsl_mc_resource_pool_add_device()
50 if (res_pool->type != pool_type) in fsl_mc_resource_pool_add_device()
52 if (res_pool->mc_bus != mc_bus) in fsl_mc_resource_pool_add_device()
55 mutex_lock(&res_pool->mutex); in fsl_mc_resource_pool_add_device()
57 if (res_pool->max_count < 0) in fsl_mc_resource_pool_add_device()
59 if (res_pool->free_count < 0 || in fsl_mc_resource_pool_add_device()
60 res_pool->free_count > res_pool->max_count) in fsl_mc_resource_pool_add_device()
75 resource->parent_pool = res_pool; in fsl_mc_resource_pool_add_device()
77 list_add_tail(&resource->node, &res_pool->free_list); in fsl_mc_resource_pool_add_device()
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/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn31/
Ddcn31_hwseq.c93 dc->res_pool->mpc->funcs->set_mpc_mem_lp_mode(dc->res_pool->mpc); in enable_memory_low_power()
96 …if (dc->debug.enable_mem_low_power.bits.vpg && dc->res_pool->stream_enc[0]->vpg->funcs->vpg_powerd… in enable_memory_low_power()
98 for (i = 0; i < dc->res_pool->stream_enc_count; i++) in enable_memory_low_power()
99 dc->res_pool->stream_enc[i]->vpg->funcs->vpg_powerdown(dc->res_pool->stream_enc[i]->vpg); in enable_memory_low_power()
101 for (i = 0; i < dc->res_pool->hpo_dp_stream_enc_count; i++) in enable_memory_low_power()
102 …dc->res_pool->hpo_dp_stream_enc[i]->vpg->funcs->vpg_powerdown(dc->res_pool->hpo_dp_stream_enc[i]->… in enable_memory_low_power()
110 struct abm **abms = dc->res_pool->multiple_abms; in dcn31_init_hw()
113 struct resource_pool *res_pool = dc->res_pool; in dcn31_init_hw() local
147 if (res_pool->dccg->funcs->dccg_init) in dcn31_init_hw()
148 res_pool->dccg->funcs->dccg_init(res_pool->dccg); in dcn31_init_hw()
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/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn201/
Ddcn201_hwseq.c183 ASSERT(opp_id_src0 < dc->res_pool->res_cap->num_opp); in dcn201_init_blank()
184 opp = dc->res_pool->opps[opp_id_src0]; in dcn201_init_blank()
225 struct resource_pool *res_pool = dc->res_pool; in dcn201_init_hw() local
228 if (res_pool->dccg->funcs->dccg_init) in dcn201_init_hw()
229 res_pool->dccg->funcs->dccg_init(res_pool->dccg); in dcn201_init_hw()
247 res_pool->ref_clocks.xtalin_clock_inKhz = in dcn201_init_hw()
251 if (res_pool->dccg && res_pool->hubbub) { in dcn201_init_hw()
252 (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg, in dcn201_init_hw()
254 &res_pool->ref_clocks.dccg_ref_clock_inKhz); in dcn201_init_hw()
256 (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub, in dcn201_init_hw()
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/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn30/
Ddcn30_hwseq.c99 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; in dcn30_set_mpc_shaper_3dlut()
194 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; in dcn30_set_output_transfer_func()
232 ASSERT(wb_info->mpcc_inst < dc->res_pool->mpcc_count); in dcn30_set_writeback()
233 mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst]; in dcn30_set_writeback()
237 dc->res_pool->mpc->funcs->set_dwb_mux(dc->res_pool->mpc, in dcn30_set_writeback()
250 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dcn30_update_writeback()
272 dwb = dc->res_pool->dwbc[wb_info[i].dwb_pipe_inst]; in dcn30_mmhubbub_warmup()
286 mcif_wb = dc->res_pool->mcif_wb[0]; in dcn30_mmhubbub_warmup()
301 dwb = dc->res_pool->dwbc[wb_info[i].dwb_pipe_inst]; in dcn30_mmhubbub_warmup()
302 mcif_wb = dc->res_pool->mcif_wb[wb_info[i].dwb_pipe_inst]; in dcn30_mmhubbub_warmup()
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/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn32/
Ddcn32_hwseq.c227 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_calculate_cab_allocation()
277 for (j = 0; j < dc->res_pool->pipe_count; j++) { in dcn32_calculate_cab_allocation()
448 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_commit_subvp_config()
479 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_subvp_pipe_control_lock()
499 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_subvp_pipe_control_lock()
521 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; in dcn32_set_mpc_shaper_3dlut()
557 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; in dcn32_set_mcm_luts()
604 struct mpc *mpc = dc->res_pool->mpc; in dcn32_set_input_transfer_func()
646 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; in dcn32_set_output_transfer_func()
683 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_subvp_update_force_pstate()
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Ddcn32_resource_helpers.c71 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_helper_calculate_num_ways_for_subvp()
84 for (j = 0; j < dc->res_pool->pipe_count; j++) { in dcn32_helper_calculate_num_ways_for_subvp()
154 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_merge_pipes_for_subvp()
173 dcn20_release_dsc(&context->res_ctx, dc->res_pool, &pipe->stream_res.dsc); in dcn32_merge_pipes_for_subvp()
199 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_all_pipes_have_stream_and_plane()
216 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_subvp_in_use()
241 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_any_surfaces_rotated()
307 for (j = 0; j < dc->res_pool->pipe_count; j++) { in dcn32_determine_det_override()
318 for (k = 0; k < dc->res_pool->pipe_count; k++) { in dcn32_determine_det_override()
327 for (k = 0; k < dc->res_pool->pipe_count; k++) { in dcn32_determine_det_override()
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/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_hwseq.c73 if (dc->res_pool->gsl_groups.gsl_0 == 0) in find_free_gsl_group()
75 if (dc->res_pool->gsl_groups.gsl_1 == 0) in find_free_gsl_group()
77 if (dc->res_pool->gsl_groups.gsl_2 == 0) in find_free_gsl_group()
123 dc->res_pool->gsl_groups.gsl_0 = 1; in dcn20_setup_gsl_group_as_lock()
127 dc->res_pool->gsl_groups.gsl_1 = 1; in dcn20_setup_gsl_group_as_lock()
131 dc->res_pool->gsl_groups.gsl_2 = 1; in dcn20_setup_gsl_group_as_lock()
149 dc->res_pool->gsl_groups.gsl_0 = 0; in dcn20_setup_gsl_group_as_lock()
153 dc->res_pool->gsl_groups.gsl_1 = 0; in dcn20_setup_gsl_group_as_lock()
157 dc->res_pool->gsl_groups.gsl_2 = 0; in dcn20_setup_gsl_group_as_lock()
302 if (opp_id_src0 >= dc->res_pool->res_cap->num_opp) { in dcn20_init_blank()
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Ddcn20_resource.c1329 const struct resource_pool *pool = dc->res_pool; in dcn20_acquire_dsc()
1382 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_add_dsc_to_stream_resource()
1417 dcn20_release_dsc(&new_ctx->res_ctx, dc->res_pool, &pipe_ctx->stream_res.dsc); in remove_dsc_from_stream_resource()
1464 const struct resource_pool *pool = dc->res_pool; in dcn20_split_stream_for_odm()
1613 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_set_mcif_arb_params()
1658 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_validate_dsc()
1728 for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) { in dcn20_find_secondary_pipe()
1751 for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) { in dcn20_find_secondary_pipe()
1773 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_merge_pipes_for_validate()
1791 dcn20_release_dsc(&context->res_ctx, dc->res_pool, &odm_pipe->stream_res.dsc); in dcn20_merge_pipes_for_validate()
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/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_hw_sequencer.c86 const uint32_t ref_clk_mhz = dc_ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000; in print_microsec()
103 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn10_lock_all_pipes()
146 dc->res_pool->hubbub->funcs->wm_read_state(dc->res_pool->hubbub, &wm); in dcn10_log_hubbub_state()
170 struct resource_pool *pool = dc->res_pool; in dcn10_log_hubp_states()
285 struct resource_pool *pool = dc->res_pool; in dcn10_log_hw_state()
754 struct hubp *hubp = dc->res_pool->hubps[0]; in undo_DEGVIDCN10_253_wa()
774 struct hubp *hubp = dc->res_pool->hubps[0]; in apply_DEGVIDCN10_253_wa()
783 for (i = 0; i < dc->res_pool->pipe_count; i++) { in apply_DEGVIDCN10_253_wa()
784 if (!dc->res_pool->hubps[i]->power_gated) in apply_DEGVIDCN10_253_wa()
811 if (dc->res_pool->hubbub->funcs->is_allow_self_refresh_enabled) in dcn10_bios_golden_init()
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Ddcn10_hw_sequencer_debug.c80 const uint32_t ref_clk_mhz = dc_ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000; in dcn10_get_hubbub_state()
84 dc->res_pool->hubbub->funcs->wm_read_state(dc->res_pool->hubbub, &wm); in dcn10_get_hubbub_state()
112 struct resource_pool *pool = dc->res_pool; in dcn10_get_hubp_states()
118 const uint32_t ref_clk_mhz = dc_ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000; in dcn10_get_hubp_states()
190 struct resource_pool *pool = dc->res_pool; in dcn10_get_rq_states()
232 struct resource_pool *pool = dc->res_pool; in dcn10_get_dlg_states()
289 struct resource_pool *pool = dc->res_pool; in dcn10_get_ttu_states()
329 struct resource_pool *pool = dc->res_pool; in dcn10_get_cm_states()
384 struct resource_pool *pool = dc->res_pool; in dcn10_get_mpcc_states()
415 struct resource_pool *pool = dc->res_pool; in dcn10_get_otg_states()
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/linux-6.1.9/drivers/gpu/drm/amd/display/dc/link/
Dlink_hwss_hpo_dp.c108 struct dccg *dccg = dc->res_pool->dccg; in setup_hpo_dp_stream_encoder()
130 struct dccg *dccg = dc->res_pool->dccg; in reset_hpo_dp_stream_encoder()
172 dc->res_pool->dccg->funcs->set_physymclk( in enable_hpo_dp_fpga_link_output()
173 dc->res_pool->dccg, in enable_hpo_dp_fpga_link_output()
177 dc->res_pool->dccg->funcs->enable_symclk32_le( in enable_hpo_dp_fpga_link_output()
178 dc->res_pool->dccg, in enable_hpo_dp_fpga_link_output()
212 dc->res_pool->dccg->funcs->disable_symclk32_le( in disable_hpo_dp_fpga_link_output()
213 dc->res_pool->dccg, in disable_hpo_dp_fpga_link_output()
215 dc->res_pool->dccg->funcs->set_physymclk( in disable_hpo_dp_fpga_link_output()
216 dc->res_pool->dccg, in disable_hpo_dp_fpga_link_output()
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/core/
Ddc.c235 for (i = 0; i < dc->res_pool->usb4_dpia_count; i++) { in create_links()
307 unsigned int num_usb4_dpia = dc->res_pool->res_cap->num_usb4_dpia; in create_link_encoders()
308 unsigned int num_dig_link_enc = dc->res_pool->res_cap->num_dig_link_enc; in create_link_encoders()
321 if (num_dig_link_enc > dc->res_pool->dig_link_enc_count) { in create_link_encoders()
323 struct link_encoder *link_enc = dc->res_pool->link_encoders[i]; in create_link_encoders()
325 if (!link_enc && dc->res_pool->funcs->link_enc_create_minimal) { in create_link_encoders()
326 link_enc = dc->res_pool->funcs->link_enc_create_minimal(dc->ctx, in create_link_encoders()
329 dc->res_pool->link_encoders[i] = link_enc; in create_link_encoders()
330 dc->res_pool->dig_link_enc_count++; in create_link_encoders()
351 if (!dc->res_pool) in destroy_link_encoders()
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Ddc_resource.c186 struct resource_pool *res_pool = NULL; in dc_create_resource_pool() local
191 res_pool = dce60_create_resource_pool( in dc_create_resource_pool()
195 res_pool = dce61_create_resource_pool( in dc_create_resource_pool()
199 res_pool = dce64_create_resource_pool( in dc_create_resource_pool()
204 res_pool = dce80_create_resource_pool( in dc_create_resource_pool()
208 res_pool = dce81_create_resource_pool( in dc_create_resource_pool()
212 res_pool = dce83_create_resource_pool( in dc_create_resource_pool()
216 res_pool = dce100_create_resource_pool( in dc_create_resource_pool()
220 res_pool = dce110_create_resource_pool( in dc_create_resource_pool()
226 res_pool = dce112_create_resource_pool( in dc_create_resource_pool()
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Ddc_link_enc_cfg.c40 for (i = 0; i < stream->ctx->dc->res_pool->res_cap->num_dig_link_enc; i++) { in is_dig_link_enc_stream()
41 link_enc = stream->ctx->dc->res_pool->link_encoders[i]; in is_dig_link_enc_stream()
159 stream->link_enc = stream->ctx->dc->res_pool->link_encoders[eng_idx]; in add_link_enc_assignment()
177 for (i = 0; i < ctx->dc->res_pool->res_cap->num_dig_link_enc; i++) { in find_first_avail_link_enc()
241 link_enc = link->dc->res_pool->link_encoders[assignment.eng_id - ENGINE_ID_DIGA]; in get_link_enc_used_by_link()
260 for (i = 0; i < dc->res_pool->res_cap->num_dig_link_enc; i++) { in clear_enc_assignments()
261 if (dc->res_pool->link_encoders[i]) in clear_enc_assignments()
299 dc->res_pool->funcs->link_enc_unassign(state, dc->current_state->streams[i]); in link_enc_cfg_link_encs_assign()
498 link_enc = link->dc->res_pool->link_encoders[assignment.eng_id - ENGINE_ID_DIGA]; in link_enc_cfg_get_link_enc_used_by_link()
523 for (i = 0; i < dc->res_pool->res_cap->num_dig_link_enc; i++) { in link_enc_cfg_get_next_avail_link_enc()
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/linux-6.1.9/drivers/gpu/drm/amd/display/dc/
Ddc_edid_parser.c35 struct dmcu *dmcu = dc->res_pool->dmcu; in dc_edid_parser_send_cea()
52 struct dmcu *dmcu = dc->res_pool->dmcu; in dc_edid_parser_recv_cea_ack()
68 struct dmcu *dmcu = dc->res_pool->dmcu; in dc_edid_parser_recv_amd_vsdb()
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn21/
Ddcn21_hwseq.c83 return dc->res_pool->hubbub->funcs->init_dchub_sys_ctx(dc->res_pool->hubbub, &config); in dcn21_init_sys_ctx()
168 struct dmcu *dmcu = pipe_ctx->stream->ctx->dc->res_pool->dmcu; in dcn21_set_abm_immediate_disable()
187 struct dmcu *dmcu = pipe_ctx->stream->ctx->dc->res_pool->dmcu; in dcn21_set_pipe()
208 if (dc->dc->res_pool->dmcu) { in dcn21_set_backlight_level()
237 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn21_is_abm_supported()
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dce110/
Ddce110_hw_sequencer.c212 unsigned int underlay_idx = dc->res_pool->underlay_pipe_index; in dce110_enable_display_power_gating()
1641 for (i = 0; i < dc->res_pool->timing_generator_count; i++) { in power_down_controllers()
1642 dc->res_pool->timing_generators[i]->funcs->disable_crtc( in power_down_controllers()
1643 dc->res_pool->timing_generators[i]); in power_down_controllers()
1651 if (dc->res_pool->dp_clock_source->funcs->cs_power_down( in power_down_clock_sources()
1652 dc->res_pool->dp_clock_source) == false) in power_down_clock_sources()
1655 for (i = 0; i < dc->res_pool->clk_src_count; i++) { in power_down_clock_sources()
1656 if (dc->res_pool->clock_sources[i]->funcs->cs_power_down( in power_down_clock_sources()
1657 dc->res_pool->clock_sources[i]) == false) in power_down_clock_sources()
1681 for (i = 0; i < dc->res_pool->timing_generator_count; i++) { in disable_vga_and_power_gate_all_controllers()
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/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn314/
Ddcn314_hwseq.c190 struct mpc *mpc = dc->res_pool->mpc; in dcn314_update_odm()
252 hws->ctx->dc->res_pool->dccg->funcs->enable_dsc && in dcn314_dsc_pg_control()
254 hws->ctx->dc->res_pool->dccg->funcs->enable_dsc( in dcn314_dsc_pg_control()
255 hws->ctx->dc->res_pool->dccg, dsc_inst); in dcn314_dsc_pg_control()
303 if (hws->ctx->dc->res_pool->dccg->funcs->disable_dsc && !power_on) in dcn314_dsc_pg_control()
304 hws->ctx->dc->res_pool->dccg->funcs->disable_dsc( in dcn314_dsc_pg_control()
305 hws->ctx->dc->res_pool->dccg, dsc_inst); in dcn314_dsc_pg_control()
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dml/dcn32/
Ddcn32_fpu.c311 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_helper_populate_phantom_dlg_params()
543 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_set_phantom_stream_timing()
612 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_get_num_free_pipes()
623 free_pipes = dc->res_pool->pipe_count - num_pipes; in dcn32_get_num_free_pipes()
658 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_assign_subvp_pipe()
733 unsigned int min_pipe_split = dc->res_pool->pipe_count + 1; // init as max number of pipes + 1 in dcn32_enough_pipes_for_subvp()
736 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_enough_pipes_for_subvp()
757 if (free_pipes >= min_pipe_split && free_pipes < dc->res_pool->pipe_count) in dcn32_enough_pipes_for_subvp()
786 for (i = 0; i < dc->res_pool->pipe_count; i++) { in subvp_subvp_schedulable()
865 for (i = 0; i < dc->res_pool->pipe_count; i++) { in subvp_drr_schedulable()
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/linux-6.1.9/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/
Ddcn20_clk_mgr.c110 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { in dcn20_update_clocks_update_dpp_dto()
152 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { in dcn20_update_clocks_update_dentist()
155 struct dccg *dccg = clk_mgr->base.ctx->dc->res_pool->dccg; in dcn20_update_clocks_update_dentist()
183 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { in dcn20_update_clocks_update_dentist()
185 struct dccg *dccg = clk_mgr->base.ctx->dc->res_pool->dccg; in dcn20_update_clocks_update_dentist()
229 struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu; in dcn2_update_clocks()
247 if (dc->res_pool->pp_smu) in dcn2_update_clocks()
248 pp_smu = &dc->res_pool->pp_smu->nv_funcs; in dcn2_update_clocks()
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dce100/
Ddce100_hw_sequencer.c112 dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool); in dce100_prepare_bandwidth()
124 dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool); in dce100_optimize_bandwidth()
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dml/dcn314/
Ddcn314_fpu.c194 dcn3_14_ip.max_num_otg = dc->res_pool->res_cap->num_timing_generator; in dcn314_update_bw_bounding_box_fpu()
195 dcn3_14_ip.max_num_dpp = dc->res_pool->pipe_count; in dcn314_update_bw_bounding_box_fpu()
296 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { in dcn314_populate_dml_pipes_from_context_fpu()
321 pipes[pipe_cnt].pipe.src.hostvm = dc->res_pool->hubbub->riommu_active; in dcn314_populate_dml_pipes_from_context_fpu()
369 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn314_populate_dml_pipes_from_context_fpu()
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dml/dcn31/
Ddcn31_fpu.c512 dc->res_pool->funcs->update_soc_for_wm_a(dc, context); in dcn31_calculate_wm_and_dlg_fp()
527 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dcn31_calculate_wm_and_dlg_fp()
570 dcn3_1_ip.max_num_otg = dc->res_pool->res_cap->num_timing_generator; in dcn31_update_bw_bounding_box()
571 dcn3_1_ip.max_num_dpp = dc->res_pool->pipe_count; in dcn31_update_bw_bounding_box()
646 dcn3_15_ip.max_num_otg = dc->res_pool->res_cap->num_timing_generator; in dcn315_update_bw_bounding_box()
647 dcn3_15_ip.max_num_dpp = dc->res_pool->pipe_count; in dcn315_update_bw_bounding_box()
718 dcn3_16_ip.max_num_otg = dc->res_pool->res_cap->num_timing_generator; in dcn316_update_bw_bounding_box()
719 dcn3_16_ip.max_num_dpp = dc->res_pool->pipe_count; in dcn316_update_bw_bounding_box()
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dce60/
Ddce60_hw_sequencer.c57 unsigned int underlay_idx = dc->res_pool->underlay_pipe_index; in dce60_should_enable_fbc()
70 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dce60_should_enable_fbc()
86 if (i == dc->res_pool->pipe_count) in dce60_should_enable_fbc()
395 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dce60_apply_ctx_for_surface()
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dml/dcn20/
Ddcn20_fpu.c887 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_populate_dml_writeback_from_context()
938 for (i = 0; i < dc->res_pool->pipe_count; i++) { in is_dtbclk_required()
955 for (i = 0; i < dc->res_pool->pipe_count; i++) { in decide_zstate_support()
976 for (i = 0; i < dc->res_pool->pipe_count; i++) { in decide_zstate_support()
1011 dc->res_pool->funcs->set_mcif_arb_params(dc, context, pipes, pipe_cnt); in dcn20_calculate_dlg_params()
1039 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_calculate_dlg_params()
1070 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_calculate_dlg_params()
1171 for (i = 0, pipe_cnt = -1; i < dc->res_pool->pipe_count; i++) { in dcn20_populate_dml_pipes_from_context()
1195 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_populate_dml_pipes_from_context()
1213 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0; in dcn20_populate_dml_pipes_from_context()
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