| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/core/ |
| D | dc_link_enc_cfg.c | 71 if (dc->current_state->res_ctx.link_enc_cfg_ctx.mode == LINK_ENC_CFG_TRANSIENT) in get_assignment()
72 assignment = dc->current_state->res_ctx.link_enc_cfg_ctx.transient_assignments[i]; in get_assignment()
74 assignment = dc->current_state->res_ctx.link_enc_cfg_ctx.link_enc_assignments[i]; in get_assignment()
88 struct link_enc_assignment assignment = state->res_ctx.link_enc_cfg_ctx.link_enc_assignments[i]; in get_stream_using_link_enc()
114 struct link_enc_assignment assignment = state->res_ctx.link_enc_cfg_ctx.link_enc_assignments[i]; in remove_link_enc_assignment()
117 state->res_ctx.link_enc_cfg_ctx.link_enc_assignments[i].valid = false; in remove_link_enc_assignment()
122 state->res_ctx.link_enc_cfg_ctx.link_enc_avail[eng_idx] = eng_id; in remove_link_enc_assignment()
125 state->res_ctx.link_enc_cfg_ctx.link_enc_assignments[i].eng_id = ENGINE_ID_UNKNOWN; in remove_link_enc_assignment()
126 state->res_ctx.link_enc_cfg_ctx.link_enc_assignments[i].stream = NULL; in remove_link_enc_assignment()
150 state->res_ctx.link_enc_cfg_ctx.link_enc_assignments[i] = (struct link_enc_assignment){ in add_link_enc_assignment()
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| D | dc_resource.c | 457 struct resource_context *res_ctx, in resource_unreference_clock_source() argument
464 res_ctx->clock_source_ref_count[i]--; in resource_unreference_clock_source()
467 res_ctx->dp_clock_source_ref_count--; in resource_unreference_clock_source()
471 struct resource_context *res_ctx, in resource_reference_clock_source() argument
478 res_ctx->clock_source_ref_count[i]++; in resource_reference_clock_source()
481 res_ctx->dp_clock_source_ref_count++; in resource_reference_clock_source()
485 struct resource_context *res_ctx, in resource_get_clock_source_reference() argument
492 return res_ctx->clock_source_ref_count[i]; in resource_get_clock_source_reference()
495 return res_ctx->dp_clock_source_ref_count; in resource_get_clock_source_reference()
632 struct resource_context *res_ctx, in resource_find_used_clk_src_for_sharing() argument
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| D | dc_stream.c | 257 struct resource_context *res_ctx; in program_cursor_attributes() local
263 res_ctx = &dc->current_state->res_ctx; in program_cursor_attributes()
266 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; in program_cursor_attributes()
363 struct resource_context *res_ctx; in program_cursor_position() local
369 res_ctx = &dc->current_state->res_ctx; in program_cursor_position()
372 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; in program_cursor_position()
564 struct resource_context *res_ctx = in dc_stream_get_vblank_counter() local
565 &dc->current_state->res_ctx; in dc_stream_get_vblank_counter()
568 struct timing_generator *tg = res_ctx->pipe_ctx[i].stream_res.tg; in dc_stream_get_vblank_counter()
570 if (res_ctx->pipe_ctx[i].stream != stream) in dc_stream_get_vblank_counter()
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| D | dc.c | 413 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i]; in dc_stream_adjust_vmin_vmax()
449 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i]; in dc_stream_get_last_used_drr_vtotal()
480 &dc->current_state->res_ctx.pipe_ctx[i]; in dc_stream_get_crtc_position()
517 pipe = &dc->current_state->res_ctx.pipe_ctx[i]; in dc_stream_forward_dmcu_crc_window()
551 pipe = &dc->current_state->res_ctx.pipe_ctx[i]; in dc_stream_stop_dmcu_crc_win_update()
596 pipe = &dc->current_state->res_ctx.pipe_ctx[i]; in dc_stream_configure_crc()
664 pipe = &dc->current_state->res_ctx.pipe_ctx[i]; in dc_stream_get_crc()
688 if (dc->current_state->res_ctx.pipe_ctx[i].stream in dc_stream_set_dyn_expansion()
690 pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; in dc_stream_set_dyn_expansion()
710 if (link->dc->current_state->res_ctx.pipe_ctx[i].stream == in dc_stream_set_dither_option()
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn32/ |
| D | dcn32_resource_helpers.c | 72 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; in dcn32_helper_calculate_num_ways_for_subvp()
85 main_pipe = &context->res_ctx.pipe_ctx[j]; in dcn32_helper_calculate_num_ways_for_subvp()
155 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; in dcn32_merge_pipes_for_subvp()
173 dcn20_release_dsc(&context->res_ctx, dc->res_pool, &pipe->stream_res.dsc); in dcn32_merge_pipes_for_subvp()
200 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; in dcn32_all_pipes_have_stream_and_plane()
217 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; in dcn32_subvp_in_use()
242 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; in dcn32_any_surfaces_rotated()
309 if (context->res_ctx.pipe_ctx[j].stream == context->streams[i] && in dcn32_determine_det_override()
317 current_plane = context->res_ctx.pipe_ctx[j].plane_state; in dcn32_determine_det_override()
319 if (k != j && context->res_ctx.pipe_ctx[k].stream == context->streams[i] && in dcn32_determine_det_override()
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| D | dcn32_resource.c | 1605 struct resource_context *res_ctx, in dcn32_acquire_post_bldn_3dlut() argument
1618 if (!res_ctx->is_mpc_3dlut_acquired[mpcc_id]) { in dcn32_acquire_post_bldn_3dlut()
1622 res_ctx->is_mpc_3dlut_acquired[mpcc_id] = true; in dcn32_acquire_post_bldn_3dlut()
1629 struct resource_context *res_ctx, in dcn32_release_post_bldn_3dlut() argument
1639 res_ctx->is_mpc_3dlut_acquired[i] = false; in dcn32_release_post_bldn_3dlut()
1657 struct pipe_ctx *curr_pipe = &context->res_ctx.pipe_ctx[dc_pipe_idx]; in dcn32_enable_phantom_plane()
1700 struct pipe_ctx *ref_pipe = &context->res_ctx.pipe_ctx[dc_pipe_idx]; in dcn32_enable_phantom_stream()
1731 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; in dcn32_remove_phantom_pipes()
1781 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; in dcn32_add_phantom_pipes()
1881 struct resource_context *res_ctx = &context->res_ctx; in dcn32_populate_dml_pipes_from_context() local
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| D | dcn32_hwseq.c | 228 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i]; in dcn32_calculate_cab_allocation()
278 struct pipe_ctx *pipe = &ctx->res_ctx.pipe_ctx[j]; in dcn32_calculate_cab_allocation()
449 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; in dcn32_commit_subvp_config()
480 pipe = &context->res_ctx.pipe_ctx[i]; in dcn32_subvp_pipe_control_lock()
500 pipe = &context->res_ctx.pipe_ctx[i]; in dcn32_subvp_pipe_control_lock()
684 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; in dcn32_subvp_update_force_pstate()
699 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; in dcn32_subvp_update_force_pstate()
725 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; in dcn32_update_mall_sel()
785 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; in dcn32_program_mall_pipe_config()
1147 struct pipe_ctx *current_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx]; in dcn32_update_odm()
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/inc/ |
| D | resource.h | 115 struct resource_context *res_ctx,
120 struct resource_context *res_ctx,
125 struct resource_context *res_ctx,
138 struct resource_context *res_ctx,
142 struct resource_context *res_ctx,
146 struct resource_context *res_ctx,
157 struct resource_context *res_ctx,
190 struct resource_context *res_ctx,
210 const struct resource_context *res_ctx,
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| D | core_types.h | 196 struct resource_context *res_ctx,
201 struct resource_context *res_ctx,
213 struct resource_context *res_ctx,
220 struct resource_context *res_ctx,
527 struct resource_context res_ctx; member
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| D | dcn20_fpu.c | 880 struct resource_context *res_ctx, in dcn20_populate_dml_writeback_from_context() argument
888 struct dc_writeback_info *wb_info = &res_ctx->pipe_ctx[i].stream->writeback_info[0]; in dcn20_populate_dml_writeback_from_context()
890 if (!res_ctx->pipe_ctx[i].stream) in dcn20_populate_dml_writeback_from_context()
932 …wb_arb_params->time_per_pixel = 16.0 * 1000 / (context->res_ctx.pipe_ctx[i].stream->phy_pix_clk / … in dcn20_fpu_set_wb_arb_params()
939 if (!context->res_ctx.pipe_ctx[i].stream) in is_dtbclk_required()
941 if (is_dp_128b_132b_signal(&context->res_ctx.pipe_ctx[i])) in is_dtbclk_required()
956 if (context->res_ctx.pipe_ctx[i].plane_state) in decide_zstate_support()
977 if (context->res_ctx.pipe_ctx[i].stream == context->streams[0] in decide_zstate_support()
978 …&& context->res_ctx.pipe_ctx[i].stream->adjust.v_total_min == context->res_ctx.pipe_ctx[i].stream-… in decide_zstate_support()
979 …&& context->res_ctx.pipe_ctx[i].stream->adjust.v_total_min > context->res_ctx.pipe_ctx[i].stream->… in decide_zstate_support()
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| D | dcn20_fpu.h | 32 struct resource_context *res_ctx,
88 struct resource_context *res_ctx,
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn20/ |
| D | dcn20_resource.c | 1311 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream); in dcn20_build_mapped_resource()
1324 struct resource_context *res_ctx, in dcn20_acquire_dsc() argument
1330 …struct display_stream_compressor *dsc_old = dc->current_state->res_ctx.pipe_ctx[pipe_idx].stream_r… in dcn20_acquire_dsc()
1338 res_ctx->is_dsc_acquired[pipe_idx] = true; in dcn20_acquire_dsc()
1343 if (dsc_old && !res_ctx->is_dsc_acquired[dsc_old->inst]) { in dcn20_acquire_dsc()
1345 res_ctx->is_dsc_acquired[dsc_old->inst] = true; in dcn20_acquire_dsc()
1351 if (!res_ctx->is_dsc_acquired[i]) { in dcn20_acquire_dsc()
1353 res_ctx->is_dsc_acquired[i] = true; in dcn20_acquire_dsc()
1358 void dcn20_release_dsc(struct resource_context *res_ctx, in dcn20_release_dsc() argument
1366 res_ctx->is_dsc_acquired[i] = false; in dcn20_release_dsc()
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| D | dcn20_resource.h | 129 void dcn20_release_dsc(struct resource_context *res_ctx,
134 struct resource_context *res_ctx,
140 struct resource_context *res_ctx,
144 struct resource_context *res_ctx,
148 struct resource_context *res_ctx,
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| D | dcn20_hwseq.c | 1742 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; in dcn20_program_front_end_for_ctx()
1743 struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; in dcn20_program_front_end_for_ctx()
1751 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; in dcn20_program_front_end_for_ctx()
1764 dcn20_detect_pipe_changes(&dc->current_state->res_ctx.pipe_ctx[i], in dcn20_program_front_end_for_ctx()
1765 &context->res_ctx.pipe_ctx[i]); in dcn20_program_front_end_for_ctx()
1769 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable in dcn20_program_front_end_for_ctx()
1770 && !context->res_ctx.pipe_ctx[i].top_pipe in dcn20_program_front_end_for_ctx()
1771 && !context->res_ctx.pipe_ctx[i].prev_odm_pipe in dcn20_program_front_end_for_ctx()
1772 && context->res_ctx.pipe_ctx[i].stream) in dcn20_program_front_end_for_ctx()
1773 hws->funcs.blank_pixel_data(dc, &context->res_ctx.pipe_ctx[i], true); in dcn20_program_front_end_for_ctx()
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn30/ |
| D | dcn30_resource.h | 75 struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes);
83 struct resource_context *res_ctx,
90 struct resource_context *res_ctx,
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| D | dcn30_resource.c | 1336 struct resource_context *res_ctx = &context->res_ctx; in dcn30_populate_dml_pipes_from_context() local
1343 if (!res_ctx->pipe_ctx[i].stream) in dcn30_populate_dml_pipes_from_context()
1354 struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes) in dcn30_populate_dml_writeback_from_context() argument
1357 dcn30_fpu_populate_dml_writeback_from_context(dc, res_ctx, pipes); in dcn30_populate_dml_writeback_from_context()
1399 if (!context->res_ctx.pipe_ctx[i].stream) in dcn30_set_mcif_arb_params()
1403 …struct dc_writeback_info *writeback_info = &context->res_ctx.pipe_ctx[i].stream->writeback_info[j]; in dcn30_set_mcif_arb_params()
1420 …wb_arb_params->time_per_pixel = (1000000 << 6) / context->res_ctx.pipe_ctx[i].stream->phy_pix_clk;… in dcn30_set_mcif_arb_params()
1443 struct resource_context *res_ctx, in dcn30_acquire_post_bldn_3dlut() argument
1458 if (!res_ctx->is_mpc_3dlut_acquired[i]) { in dcn30_acquire_post_bldn_3dlut()
1462 res_ctx->is_mpc_3dlut_acquired[i] = true; in dcn30_acquire_post_bldn_3dlut()
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| D | dcn32_fpu.c | 312 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; in dcn32_helper_populate_phantom_dlg_params()
544 pipe = &context->res_ctx.pipe_ctx[i]; in dcn32_set_phantom_stream_timing()
613 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; in dcn32_get_num_free_pipes()
659 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; in dcn32_assign_subvp_pipe()
685 pipe = &context->res_ctx.pipe_ctx[i]; in dcn32_assign_subvp_pipe()
737 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; in dcn32_enough_pipes_for_subvp()
787 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; in subvp_subvp_schedulable()
866 pipe = &context->res_ctx.pipe_ctx[i]; in subvp_drr_schedulable()
947 pipe = &context->res_ctx.pipe_ctx[i]; in subvp_vblank_schedulable()
964 if (found && context->res_ctx.pipe_ctx[vblank_index].stream->ignore_msa_timing_param) { in subvp_vblank_schedulable()
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dce60/ |
| D | dce60_hw_sequencer.c | 56 struct resource_context *res_ctx = &context->res_ctx; in dce60_should_enable_fbc() local
71 if (res_ctx->pipe_ctx[i].stream) { in dce60_should_enable_fbc()
73 pipe_ctx = &res_ctx->pipe_ctx[i]; in dce60_should_enable_fbc()
124 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx]; in dce60_enable_fbc()
396 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; in dce60_apply_ctx_for_surface()
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dce110/ |
| D | dce110_hw_sequencer.c | 1097 if (dc->current_state->res_ctx.pipe_ctx[i].stream_res.audio != NULL) in dce110_enable_audio_stream()
1421 struct pipe_ctx *pipe_ctx_old = &dc->current_state->res_ctx. in dce110_enable_stream_timing()
1693 dc->current_state->res_ctx.pipe_ctx[i].pipe_idx = i; in disable_vga_and_power_gate_all_controllers()
1695 &dc->current_state->res_ctx.pipe_ctx[i]); in disable_vga_and_power_gate_all_controllers()
1849 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; in dce110_set_displaymarks()
1878 struct resource_context *res_ctx, in dce110_set_safe_displaymarks() argument
1890 if (res_ctx->pipe_ctx[i].stream == NULL || res_ctx->pipe_ctx[i].plane_res.mi == NULL) in dce110_set_safe_displaymarks()
1893 res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_display_marks( in dce110_set_safe_displaymarks()
1894 res_ctx->pipe_ctx[i].plane_res.mi, in dce110_set_safe_displaymarks()
1902 res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_chroma_display_marks( in dce110_set_safe_displaymarks()
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| D | dce110_resource.h | 49 struct resource_context *res_ctx,
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dce100/ |
| D | dce100_hw_sequencer.c | 112 dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool); in dce100_prepare_bandwidth()
124 dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool); in dce100_optimize_bandwidth()
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| D | dce100_resource.h | 50 struct resource_context *res_ctx,
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dml/dcn314/ |
| D | dcn314_fpu.c | 288 struct resource_context *res_ctx = &context->res_ctx; in dcn314_populate_dml_pipes_from_context_fpu() local
299 if (!res_ctx->pipe_ctx[i].stream) in dcn314_populate_dml_pipes_from_context_fpu()
301 pipe = &res_ctx->pipe_ctx[i]; in dcn314_populate_dml_pipes_from_context_fpu()
370 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; in dcn314_populate_dml_pipes_from_context_fpu()
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dce/ |
| D | dmub_psr.c | 308 struct resource_context *res_ctx = &link->ctx->dc->current_state->res_ctx; in dmub_psr_copy_settings() local
312 if (res_ctx->pipe_ctx[i].stream && in dmub_psr_copy_settings()
313 res_ctx->pipe_ctx[i].stream->link == link && in dmub_psr_copy_settings()
314 res_ctx->pipe_ctx[i].stream->link->connector_signal == SIGNAL_TYPE_EDP) { in dmub_psr_copy_settings()
315 pipe_ctx = &res_ctx->pipe_ctx[i]; in dmub_psr_copy_settings()
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn10/ |
| D | dcn10_resource.h | 50 struct resource_context *res_ctx,
|