| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn302/ |
| D | dcn302_resource.c | 716 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn302_dwbc_create()
751 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn302_mmhubbub_create()
1019 for (i = 0; i < pool->res_cap->num_dsc; i++) { in dcn302_resource_destruct()
1049 for (i = 0; i < pool->res_cap->num_ddc; i++) { in dcn302_resource_destruct()
1062 for (i = 0; i < pool->res_cap->num_opp; i++) { in dcn302_resource_destruct()
1067 for (i = 0; i < pool->res_cap->num_timing_generator; i++) { in dcn302_resource_destruct()
1074 for (i = 0; i < pool->res_cap->num_dwb; i++) { in dcn302_resource_destruct()
1098 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { in dcn302_resource_destruct()
1207 pool->res_cap = &res_cap_dcn302; in dcn302_resource_construct()
1215 pool->pipe_count = pool->res_cap->num_timing_generator; in dcn302_resource_construct()
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn303/ |
| D | dcn303_resource.c | 660 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn303_dwbc_create()
695 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn303_mmhubbub_create()
946 for (i = 0; i < pool->res_cap->num_dsc; i++) { in dcn303_resource_destruct()
976 for (i = 0; i < pool->res_cap->num_ddc; i++) { in dcn303_resource_destruct()
989 for (i = 0; i < pool->res_cap->num_opp; i++) { in dcn303_resource_destruct()
994 for (i = 0; i < pool->res_cap->num_timing_generator; i++) { in dcn303_resource_destruct()
1001 for (i = 0; i < pool->res_cap->num_dwb; i++) { in dcn303_resource_destruct()
1025 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { in dcn303_resource_destruct()
1136 pool->res_cap = &res_cap_dcn303; in dcn303_resource_construct()
1144 pool->pipe_count = pool->res_cap->num_timing_generator; in dcn303_resource_construct()
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn301/ |
| D | dcn301_resource.c | 1077 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn301_destruct()
1107 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn301_destruct()
1120 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn301_destruct()
1125 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn301_destruct()
1132 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn301_destruct()
1155 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { in dcn301_destruct()
1171 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn301_destruct()
1200 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn301_dwbc_create()
1225 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn301_mmhubbub_create()
1323 loaded_ip->max_num_otg = pool->base.res_cap->num_timing_generator; in init_soc_bounding_box()
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn314/ |
| D | dcn314_resource.c | 1156 if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) in dcn31_link_enc_create_minimal()
1437 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn314_resource_destruct()
1466 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn314_resource_destruct()
1479 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn314_resource_destruct()
1484 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn314_resource_destruct()
1491 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn314_resource_destruct()
1514 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { in dcn314_resource_destruct()
1530 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn314_resource_destruct()
1564 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_dwbc_create()
1589 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_mmhubbub_create()
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn315/ |
| D | dcn315_resource.c | 1126 if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) in dcn31_link_enc_create_minimal()
1408 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn315_resource_destruct()
1438 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn315_resource_destruct()
1451 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn315_resource_destruct()
1456 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn315_resource_destruct()
1463 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn315_resource_destruct()
1486 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { in dcn315_resource_destruct()
1502 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn315_resource_destruct()
1536 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_dwbc_create()
1561 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_mmhubbub_create()
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn316/ |
| D | dcn316_resource.c | 1125 if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) in dcn31_link_enc_create_minimal()
1409 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn316_resource_destruct()
1439 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn316_resource_destruct()
1452 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn316_resource_destruct()
1457 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn316_resource_destruct()
1464 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn316_resource_destruct()
1487 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { in dcn316_resource_destruct()
1503 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn316_resource_destruct()
1537 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_dwbc_create()
1562 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_mmhubbub_create()
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn31/ |
| D | dcn31_resource.c | 1130 if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) in dcn31_link_enc_create_minimal()
1410 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn31_resource_destruct()
1440 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn31_resource_destruct()
1453 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn31_resource_destruct()
1458 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn31_resource_destruct()
1465 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn31_resource_destruct()
1488 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { in dcn31_resource_destruct()
1504 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn31_resource_destruct()
1538 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_dwbc_create()
1563 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_mmhubbub_create()
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn321/ |
| D | dcn321_resource.c | 1388 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn321_resource_destruct()
1417 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn321_resource_destruct()
1430 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn321_resource_destruct()
1435 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn321_resource_destruct()
1442 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn321_resource_destruct()
1465 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { in dcn321_resource_destruct()
1481 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn321_resource_destruct()
1500 uint32_t dwb_count = pool->res_cap->num_dwb; in dcn321_dwbc_create()
1529 uint32_t dwb_count = pool->res_cap->num_dwb; in dcn321_mmhubbub_create()
1663 pool->base.res_cap = &res_cap_dcn321; in dcn321_resource_construct()
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn30/ |
| D | dcn30_resource.c | 1099 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn30_resource_destruct()
1129 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn30_resource_destruct()
1142 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn30_resource_destruct()
1147 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn30_resource_destruct()
1154 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn30_resource_destruct()
1177 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { in dcn30_resource_destruct()
1230 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn30_dwbc_create()
1255 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn30_mmhubbub_create()
1457 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { in dcn30_acquire_post_bldn_3dlut()
1487 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { in dcn30_release_post_bldn_3dlut()
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| D | dcn30_hwseq.c | 390 ASSERT(stream->num_wb_info <= dc->res_pool->res_cap->num_dwb); in dcn30_program_all_writeback_pipes_in_tree()
420 ASSERT(wb_info.dwb_pipe_inst < dc->res_pool->res_cap->num_dwb); in dcn30_program_all_writeback_pipes_in_tree()
538 for (i = 0; i < res_pool->res_cap->num_dsc; i++) in dcn30_init_hw()
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dce60/ |
| D | dce60_resource.c | 372 static const struct resource_caps res_cap = { variable
822 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce60_resource_destruct()
952 pool->base.res_cap = &res_cap; in dce60_construct()
960 pool->base.pipe_count = res_cap.num_timing_generator; in dce60_construct()
961 pool->base.timing_generator_count = res_cap.num_timing_generator; in dce60_construct()
1073 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce60_construct()
1147 pool->base.res_cap = &res_cap_61; in dce61_construct()
1271 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce61_construct()
1345 pool->base.res_cap = &res_cap_64; in dce64_construct()
1465 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce64_construct()
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dce80/ |
| D | dce80_resource.c | 375 static const struct resource_caps res_cap = { variable
825 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce80_resource_destruct()
955 pool->base.res_cap = &res_cap; in dce80_construct()
963 pool->base.pipe_count = res_cap.num_timing_generator; in dce80_construct()
964 pool->base.timing_generator_count = res_cap.num_timing_generator; in dce80_construct()
1082 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce80_construct()
1156 pool->base.res_cap = &res_cap_81; in dce81_construct()
1282 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce81_construct()
1356 pool->base.res_cap = &res_cap_83; in dce83_construct()
1478 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce83_construct()
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn32/ |
| D | dcn32_resource.c | 1402 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn32_resource_destruct()
1432 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn32_resource_destruct()
1445 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn32_resource_destruct()
1450 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn32_resource_destruct()
1457 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn32_resource_destruct()
1480 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { in dcn32_resource_destruct()
1496 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn32_resource_destruct()
1515 uint32_t dwb_count = pool->res_cap->num_dwb; in dcn32_dwbc_create()
1544 uint32_t dwb_count = pool->res_cap->num_dwb; in dcn32_mmhubbub_create()
1637 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { in dcn32_release_post_bldn_3dlut()
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dce100/ |
| D | dce100_resource.c | 374 static const struct resource_caps res_cap = { variable
777 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce100_resource_destruct()
989 pool->base.res_cap = &res_cap; in dce100_resource_construct()
1064 pool->base.pipe_count = res_cap.num_timing_generator; in dce100_resource_construct()
1065 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; in dce100_resource_construct()
1120 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce100_resource_construct()
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn20/ |
| D | dcn20_resource.c | 1113 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn20_resource_destruct()
1143 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn20_resource_destruct()
1156 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn20_resource_destruct()
1161 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn20_resource_destruct()
1168 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn20_resource_destruct()
1336 if (pool->res_cap->num_dsc == pool->res_cap->num_opp) { in dcn20_acquire_dsc()
1350 for (i = 0; i < pool->res_cap->num_dsc; i++) in dcn20_acquire_dsc()
1364 for (i = 0; i < pool->res_cap->num_dsc; i++) in dcn20_release_dsc()
2232 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn20_dwbc_create()
2255 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn20_mmhubbub_create()
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/core/ |
| D | dc_link_enc_cfg.c | 40 for (i = 0; i < stream->ctx->dc->res_pool->res_cap->num_dig_link_enc; i++) { in is_dig_link_enc_stream()
177 for (i = 0; i < ctx->dc->res_pool->res_cap->num_dig_link_enc; i++) { in find_first_avail_link_enc()
260 for (i = 0; i < dc->res_pool->res_cap->num_dig_link_enc; i++) { in clear_enc_assignments()
523 for (i = 0; i < dc->res_pool->res_cap->num_dig_link_enc; i++) { in link_enc_cfg_get_next_avail_link_enc()
690 for (j = 0; j < dc->res_pool->res_cap->num_dig_link_enc; j++) { in link_enc_cfg_validate()
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn21/ |
| D | dcn21_resource.c | 705 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn21_resource_destruct()
735 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn21_resource_destruct()
748 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn21_resource_destruct()
753 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn21_resource_destruct()
760 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn21_resource_destruct()
1437 pool->base.res_cap = &res_cap_rn; in dcn21_resource_construct()
1441 pool->base.res_cap = &res_cap_rn_FPGA_4pipe; in dcn21_resource_construct()
1452 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dcn21_resource_construct()
1670 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn21_resource_construct()
1706 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn21_resource_construct()
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dce120/ |
| D | dce120_resource.c | 497 static const struct resource_caps res_cap = { variable
624 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce120_resource_destruct()
1066 pool->base.res_cap = &res_cap; in dce120_resource_construct()
1070 pool->base.pipe_count = res_cap.num_timing_generator; in dce120_resource_construct()
1071 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; in dce120_resource_construct()
1216 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce120_resource_construct()
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn201/ |
| D | dcn201_resource.c | 953 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn201_resource_destruct()
958 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn201_resource_destruct()
1095 pool->base.res_cap = &res_cap_dnc201; in dcn201_resource_construct()
1193 dcn201_ip.max_num_otg = pool->base.res_cap->num_timing_generator; in dcn201_resource_construct()
1228 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn201_resource_construct()
1237 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn201_resource_construct()
1253 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn201_resource_construct()
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| D | dcn201_hwseq.c | 183 ASSERT(opp_id_src0 < dc->res_pool->res_cap->num_opp); in dcn201_init_blank()
307 for (i = 0; i < res_pool->res_cap->num_opp; i++) { in dcn201_init_hw()
340 for (i = 0; i < res_pool->res_cap->num_dwb; i++) in dcn201_init_hw()
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn10/ |
| D | dcn10_resource.c | 485 static const struct resource_caps res_cap = { variable
959 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn10_resource_destruct()
1370 pool->base.res_cap = &rv2_res_cap; in dcn10_resource_construct()
1372 pool->base.res_cap = &res_cap; in dcn10_resource_construct()
1386 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dcn10_resource_construct()
1653 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn10_resource_construct()
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dce112/ |
| D | dce112_resource.c | 798 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce112_resource_destruct()
1226 pool->base.res_cap = dce112_resource_cap(&ctx->asic_id); in dce112_resource_construct()
1233 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dce112_resource_construct()
1234 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; in dce112_resource_construct()
1367 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce112_resource_construct()
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dce110/ |
| D | dce110_resource.c | 836 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce110_resource_destruct()
1357 pool->base.res_cap = dce110_resource_cap(&ctx->asic_id); in dce110_resource_construct()
1364 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dce110_resource_construct()
1366 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; in dce110_resource_construct()
1481 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce110_resource_construct()
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| D | dcn31_fpu.c | 570 dcn3_1_ip.max_num_otg = dc->res_pool->res_cap->num_timing_generator; in dcn31_update_bw_bounding_box()
646 dcn3_15_ip.max_num_otg = dc->res_pool->res_cap->num_timing_generator; in dcn315_update_bw_bounding_box()
718 dcn3_16_ip.max_num_otg = dc->res_pool->res_cap->num_timing_generator; in dcn316_update_bw_bounding_box()
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/inc/ |
| D | core_types.h | 328 const struct resource_caps *res_cap; member
|