| /linux-6.1.9/drivers/net/ethernet/samsung/sxgbe/ |
| D | sxgbe_mtl.c | 23 u32 reg_val; in sxgbe_mtl_init() local
25 reg_val = readl(ioaddr + SXGBE_MTL_OP_MODE_REG); in sxgbe_mtl_init()
26 reg_val &= ETS_RST; in sxgbe_mtl_init()
31 reg_val &= ETS_WRR; in sxgbe_mtl_init()
34 reg_val |= ETS_WFQ; in sxgbe_mtl_init()
37 reg_val |= ETS_DWRR; in sxgbe_mtl_init()
40 writel(reg_val, ioaddr + SXGBE_MTL_OP_MODE_REG); in sxgbe_mtl_init()
44 reg_val &= RAA_SP; in sxgbe_mtl_init()
47 reg_val |= RAA_WSP; in sxgbe_mtl_init()
50 writel(reg_val, ioaddr + SXGBE_MTL_OP_MODE_REG); in sxgbe_mtl_init()
[all …]
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| /linux-6.1.9/drivers/input/keyboard/ |
| D | imx_keypad.c | 83 unsigned short reg_val; in imx_keypad_scan_matrix() local
94 reg_val = readw(keypad->mmio_base + KPDR); in imx_keypad_scan_matrix()
95 reg_val |= 0xff00; in imx_keypad_scan_matrix()
96 writew(reg_val, keypad->mmio_base + KPDR); in imx_keypad_scan_matrix()
98 reg_val = readw(keypad->mmio_base + KPCR); in imx_keypad_scan_matrix()
99 reg_val &= ~((keypad->cols_en_mask & 0xff) << 8); in imx_keypad_scan_matrix()
100 writew(reg_val, keypad->mmio_base + KPCR); in imx_keypad_scan_matrix()
104 reg_val = readw(keypad->mmio_base + KPCR); in imx_keypad_scan_matrix()
105 reg_val |= (keypad->cols_en_mask & 0xff) << 8; in imx_keypad_scan_matrix()
106 writew(reg_val, keypad->mmio_base + KPCR); in imx_keypad_scan_matrix()
[all …]
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| /linux-6.1.9/drivers/net/ethernet/marvell/octeon_ep/ |
| D | octep_cn9k_pf.c | 245 u64 reg_val; in octep_setup_iq_regs_cn93_pf() local
248 reg_val = octep_read_csr64(oct, CN93_SDP_R_IN_CONTROL(iq_no)); in octep_setup_iq_regs_cn93_pf()
251 if (!(reg_val & CN93_R_IN_CTL_IDLE)) { in octep_setup_iq_regs_cn93_pf()
253 reg_val = octep_read_csr64(oct, CN93_SDP_R_IN_CONTROL(iq_no)); in octep_setup_iq_regs_cn93_pf()
254 } while (!(reg_val & CN93_R_IN_CTL_IDLE)); in octep_setup_iq_regs_cn93_pf()
257 reg_val |= CN93_R_IN_CTL_RDSIZE; in octep_setup_iq_regs_cn93_pf()
258 reg_val |= CN93_R_IN_CTL_IS_64B; in octep_setup_iq_regs_cn93_pf()
259 reg_val |= CN93_R_IN_CTL_ESR; in octep_setup_iq_regs_cn93_pf()
260 octep_write_csr64(oct, CN93_SDP_R_IN_CONTROL(iq_no), reg_val); in octep_setup_iq_regs_cn93_pf()
283 reg_val = CFG_GET_IQ_INTR_THRESHOLD(oct->conf) & 0xffffffff; in octep_setup_iq_regs_cn93_pf()
[all …]
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| /linux-6.1.9/drivers/media/dvb-frontends/ |
| D | af9033_priv.h | 19 struct reg_val { struct
87 static const struct reg_val ofsm_init[] = {
202 static const struct reg_val tuner_init_tua9001[] = {
246 static const struct reg_val tuner_init_fc0011[] = {
309 static const struct reg_val tuner_init_fc0012[] = {
354 static const struct reg_val tuner_init_mxl5007t[] = {
391 static const struct reg_val tuner_init_tda18218[] = {
427 static const struct reg_val tuner_init_fc2580[] = {
467 static const struct reg_val ofsm_init_it9135_v1[] = {
582 static const struct reg_val tuner_init_it9135_38[] = {
[all …]
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/ |
| D | dc_helper.c | 166 uint32_t reg_val) in dmub_reg_value_burst_set_pack() argument
184 cmd_buf->write_values[offload->reg_seq_count] = reg_val; in dmub_reg_value_burst_set_pack()
249 uint32_t reg_val; in generic_reg_update_ex() local
265 reg_val = dm_read_reg(ctx, addr); in generic_reg_update_ex()
266 reg_val = (reg_val & ~field_value_mask.mask) | field_value_mask.value; in generic_reg_update_ex()
267 dm_write_reg(ctx, addr, reg_val); in generic_reg_update_ex()
268 return reg_val; in generic_reg_update_ex()
272 uint32_t addr, uint32_t reg_val, int n, in generic_reg_set_ex() argument
288 reg_val = (reg_val & ~field_value_mask.mask) | field_value_mask.value; in generic_reg_set_ex()
292 return dmub_reg_value_burst_set_pack(ctx, addr, reg_val); in generic_reg_set_ex()
[all …]
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| /linux-6.1.9/drivers/spi/ |
| D | spi-mt65xx.c | 271 u32 reg_val; in mtk_spi_reset() local
274 reg_val = readl(mdata->base + SPI_CMD_REG); in mtk_spi_reset()
275 reg_val |= SPI_CMD_RST; in mtk_spi_reset()
276 writel(reg_val, mdata->base + SPI_CMD_REG); in mtk_spi_reset()
278 reg_val = readl(mdata->base + SPI_CMD_REG); in mtk_spi_reset()
279 reg_val &= ~SPI_CMD_RST; in mtk_spi_reset()
280 writel(reg_val, mdata->base + SPI_CMD_REG); in mtk_spi_reset()
290 u32 reg_val; in mtk_spi_set_hw_cs_timing() local
309 reg_val = readl(mdata->base + SPI_CFG0_REG); in mtk_spi_set_hw_cs_timing()
313 reg_val &= ~(0xffff << SPI_ADJUST_CFG0_CS_HOLD_OFFSET); in mtk_spi_set_hw_cs_timing()
[all …]
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| D | spi-slave-mt27xx.c | 100 u32 reg_val; in mtk_spi_slave_disable_dma() local
102 reg_val = readl(mdata->base + SPIS_DMA_CFG_REG); in mtk_spi_slave_disable_dma()
103 reg_val &= ~RX_DMA_EN; in mtk_spi_slave_disable_dma()
104 reg_val &= ~TX_DMA_EN; in mtk_spi_slave_disable_dma()
105 writel(reg_val, mdata->base + SPIS_DMA_CFG_REG); in mtk_spi_slave_disable_dma()
110 u32 reg_val; in mtk_spi_slave_disable_xfer() local
112 reg_val = readl(mdata->base + SPIS_CFG_REG); in mtk_spi_slave_disable_xfer()
113 reg_val &= ~SPIS_TX_EN; in mtk_spi_slave_disable_xfer()
114 reg_val &= ~SPIS_RX_EN; in mtk_spi_slave_disable_xfer()
115 writel(reg_val, mdata->base + SPIS_CFG_REG); in mtk_spi_slave_disable_xfer()
[all …]
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| /linux-6.1.9/drivers/gpu/drm/msm/disp/dpu1/ |
| D | dpu_hw_vbif.c | 61 u32 reg_val; in dpu_hw_set_mem_type() local
79 reg_val = DPU_REG_READ(c, reg_off); in dpu_hw_set_mem_type()
80 reg_val &= ~(0x7 << bit_off); in dpu_hw_set_mem_type()
81 reg_val |= (value & 0x7) << bit_off; in dpu_hw_set_mem_type()
82 DPU_REG_WRITE(c, reg_off, reg_val); in dpu_hw_set_mem_type()
89 u32 reg_val; in dpu_hw_set_limit_conf() local
100 reg_val = DPU_REG_READ(c, reg_off); in dpu_hw_set_limit_conf()
101 reg_val &= ~(0xFF << bit_off); in dpu_hw_set_limit_conf()
102 reg_val |= (limit) << bit_off; in dpu_hw_set_limit_conf()
103 DPU_REG_WRITE(c, reg_off, reg_val); in dpu_hw_set_limit_conf()
[all …]
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| /linux-6.1.9/drivers/net/ethernet/allwinner/ |
| D | sun4i-emac.c | 105 unsigned int reg_val; in emac_update_speed() local
108 reg_val = readl(db->membase + EMAC_MAC_SUPP_REG); in emac_update_speed()
109 reg_val &= ~EMAC_MAC_SUPP_100M; in emac_update_speed()
111 reg_val |= EMAC_MAC_SUPP_100M; in emac_update_speed()
112 writel(reg_val, db->membase + EMAC_MAC_SUPP_REG); in emac_update_speed()
118 unsigned int reg_val; in emac_update_duplex() local
121 reg_val = readl(db->membase + EMAC_MAC_CTL1_REG); in emac_update_duplex()
122 reg_val &= ~EMAC_MAC_CTL1_DUPLEX_EN; in emac_update_duplex()
124 reg_val |= EMAC_MAC_CTL1_DUPLEX_EN; in emac_update_duplex()
125 writel(reg_val, db->membase + EMAC_MAC_CTL1_REG); in emac_update_duplex()
[all …]
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| /linux-6.1.9/sound/drivers/opl3/ |
| D | opl3_synth.c | 396 unsigned char reg_val; in snd_opl3_play_note() local
416 reg_val = (unsigned char) note->fnum; in snd_opl3_play_note()
418 opl3->command(opl3, opl3_reg, reg_val); in snd_opl3_play_note()
420 reg_val = 0x00; in snd_opl3_play_note()
423 reg_val |= OPL3_KEYON_BIT; in snd_opl3_play_note()
425 reg_val |= (note->octave << 2) & OPL3_BLOCKNUM_MASK; in snd_opl3_play_note()
427 reg_val |= (unsigned char) (note->fnum >> 8) & OPL3_FNUM_HIGH_MASK; in snd_opl3_play_note()
431 opl3->command(opl3, opl3_reg, reg_val); in snd_opl3_play_note()
444 unsigned char reg_val; in snd_opl3_set_voice() local
470 reg_val = 0x00; in snd_opl3_set_voice()
[all …]
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| /linux-6.1.9/arch/arm/mach-qcom/ |
| D | platsmp.c | 84 u32 reg_val; in cortex_a7_release_secondary() local
103 reg_val = CORE_RST | COREPOR_RST | CLAMP | CORE_MEM_CLAMP; in cortex_a7_release_secondary()
104 writel(reg_val, reg + APCS_CPU_PWR_CTL); in cortex_a7_release_secondary()
111 reg_val &= ~CORE_MEM_CLAMP; in cortex_a7_release_secondary()
112 writel(reg_val, reg + APCS_CPU_PWR_CTL); in cortex_a7_release_secondary()
113 reg_val |= L2DT_SLP; in cortex_a7_release_secondary()
114 writel(reg_val, reg + APCS_CPU_PWR_CTL); in cortex_a7_release_secondary()
117 reg_val = (reg_val | BIT(17)) & ~CLAMP; in cortex_a7_release_secondary()
118 writel(reg_val, reg + APCS_CPU_PWR_CTL); in cortex_a7_release_secondary()
122 reg_val &= ~(CORE_RST | COREPOR_RST); in cortex_a7_release_secondary()
[all …]
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| /linux-6.1.9/drivers/gpu/drm/msm/hdmi/ |
| D | hdmi_hdcp.c | 45 u32 reg_val; member
199 u32 reg_val, hdcp_int_status; in msm_hdmi_hdcp_irq() local
203 reg_val = hdmi_read(hdmi, REG_HDMI_HDCP_INT_CTRL); in msm_hdmi_hdcp_irq()
204 hdcp_int_status = reg_val & HDCP_INT_STATUS_MASK; in msm_hdmi_hdcp_irq()
210 reg_val |= hdcp_int_status << 1; in msm_hdmi_hdcp_irq()
213 reg_val |= HDMI_HDCP_INT_CTRL_AUTH_FAIL_INFO_ACK; in msm_hdmi_hdcp_irq()
214 hdmi_write(hdmi, REG_HDMI_HDCP_INT_CTRL, reg_val); in msm_hdmi_hdcp_irq()
228 reg_val = hdmi_read(hdmi, REG_HDMI_HDCP_LINK0_STATUS); in msm_hdmi_hdcp_irq()
230 __func__, reg_val); in msm_hdmi_hdcp_irq()
284 u32 reg_val, failure, nack0; in msm_reset_hdcp_ddc_failures() local
[all …]
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| /linux-6.1.9/arch/powerpc/platforms/powernv/ |
| D | opal-fadump.h | 83 __be64 reg_val; member
88 u64 reg_val) in opal_fadump_set_regval_regnum() argument
92 regs->gpr[reg_num] = reg_val; in opal_fadump_set_regval_regnum()
98 regs->ctr = reg_val; in opal_fadump_set_regval_regnum()
101 regs->link = reg_val; in opal_fadump_set_regval_regnum()
104 regs->xer = reg_val; in opal_fadump_set_regval_regnum()
107 regs->dar = reg_val; in opal_fadump_set_regval_regnum()
110 regs->dsisr = reg_val; in opal_fadump_set_regval_regnum()
113 regs->nip = reg_val; in opal_fadump_set_regval_regnum()
116 regs->msr = reg_val; in opal_fadump_set_regval_regnum()
[all …]
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| /linux-6.1.9/arch/mips/pci/ |
| D | fixup-malta.c | 70 unsigned char reg_val; in malta_piix_func0_fixup() local
84 pci_read_config_byte(pdev, PIIX4_FUNC0_PIRQRC+i, ®_val); in malta_piix_func0_fixup()
85 if (reg_val & PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_DISABLE) in malta_piix_func0_fixup()
88 pci_irq[PCIA+i] = piixirqmap[reg_val & in malta_piix_func0_fixup()
98 pci_read_config_byte(pdev, PIIX4_FUNC0_TOM, ®_val); in malta_piix_func0_fixup()
99 pci_write_config_byte(pdev, PIIX4_FUNC0_TOM, reg_val | in malta_piix_func0_fixup()
109 pci_read_config_byte(pdev, PIIX4_FUNC0_SERIRQC, ®_val); in malta_piix_func0_fixup()
110 reg_val |= PIIX4_FUNC0_SERIRQC_EN | PIIX4_FUNC0_SERIRQC_CONT; in malta_piix_func0_fixup()
111 pci_write_config_byte(pdev, PIIX4_FUNC0_SERIRQC, reg_val); in malta_piix_func0_fixup()
124 unsigned char reg_val; in malta_piix_func1_fixup() local
[all …]
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| /linux-6.1.9/drivers/ata/ |
| D | ahci_sunxi.c | 55 u32 reg_val; in sunxi_clrbits() local
57 reg_val = readl(reg); in sunxi_clrbits()
58 reg_val &= ~(clr_val); in sunxi_clrbits()
59 writel(reg_val, reg); in sunxi_clrbits()
64 u32 reg_val; in sunxi_setbits() local
66 reg_val = readl(reg); in sunxi_setbits()
67 reg_val |= set_val; in sunxi_setbits()
68 writel(reg_val, reg); in sunxi_setbits()
73 u32 reg_val; in sunxi_clrsetbits() local
75 reg_val = readl(reg); in sunxi_clrsetbits()
[all …]
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| /linux-6.1.9/drivers/hwmon/ |
| D | ltc2992.c | 409 int reg_val; in ltc2992_get_voltage() local
411 reg_val = ltc2992_read_reg(st, reg, 2); in ltc2992_get_voltage()
412 if (reg_val < 0) in ltc2992_get_voltage()
413 return reg_val; in ltc2992_get_voltage()
415 reg_val = reg_val >> 4; in ltc2992_get_voltage()
416 *val = DIV_ROUND_CLOSEST(reg_val * scale, 1000); in ltc2992_get_voltage()
431 int reg_val; in ltc2992_read_gpio_alarm() local
439 reg_val = ltc2992_read_reg(st, ltc2992_gpio_addr_map[nr_gpio].alarm, 1); in ltc2992_read_gpio_alarm()
440 if (reg_val < 0) in ltc2992_read_gpio_alarm()
441 return reg_val; in ltc2992_read_gpio_alarm()
[all …]
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| /linux-6.1.9/drivers/net/ethernet/cavium/liquidio/ |
| D | cn23xx_vf_device.c | 68 u64 reg_val = octeon_read_csr64(oct, in cn23xx_vf_reset_io_queues() local
70 while ((READ_ONCE(reg_val) & CN23XX_PKT_INPUT_CTL_RST) && in cn23xx_vf_reset_io_queues()
71 !(READ_ONCE(reg_val) & CN23XX_PKT_INPUT_CTL_QUIET) && in cn23xx_vf_reset_io_queues()
73 WRITE_ONCE(reg_val, octeon_read_csr64( in cn23xx_vf_reset_io_queues()
83 WRITE_ONCE(reg_val, READ_ONCE(reg_val) & in cn23xx_vf_reset_io_queues()
86 READ_ONCE(reg_val)); in cn23xx_vf_reset_io_queues()
88 WRITE_ONCE(reg_val, octeon_read_csr64( in cn23xx_vf_reset_io_queues()
90 if (READ_ONCE(reg_val) & CN23XX_PKT_INPUT_CTL_RST) { in cn23xx_vf_reset_io_queues()
153 u32 reg_val; in cn23xx_vf_setup_global_output_regs() local
160 reg_val = in cn23xx_vf_setup_global_output_regs()
[all …]
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| /linux-6.1.9/sound/soc/amd/raven/ |
| D | acp3x-i2s.c | 81 u32 reg_val, frmt_reg; in acp3x_i2s_hwparams() local
116 reg_val = mmACP_BTTDM_ITER; in acp3x_i2s_hwparams()
121 reg_val = mmACP_I2STDM_ITER; in acp3x_i2s_hwparams()
127 reg_val = mmACP_BTTDM_IRER; in acp3x_i2s_hwparams()
132 reg_val = mmACP_I2STDM_IRER; in acp3x_i2s_hwparams()
137 val = rv_readl(rtd->acp3x_base + reg_val); in acp3x_i2s_hwparams()
138 rv_writel(val | 0x2, rtd->acp3x_base + reg_val); in acp3x_i2s_hwparams()
141 val = rv_readl(rtd->acp3x_base + reg_val); in acp3x_i2s_hwparams()
144 rv_writel(val, rtd->acp3x_base + reg_val); in acp3x_i2s_hwparams()
152 u32 ret, val, period_bytes, reg_val, ier_val, water_val; in acp3x_i2s_trigger() local
[all …]
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| /linux-6.1.9/drivers/video/backlight/ |
| D | lm3639_bl.c | 50 unsigned int reg_val; in lm3639_chip_init() local
60 reg_val = (pdata->pin_pwm & 0x40) | pdata->pin_strobe | pdata->pin_tx; in lm3639_chip_init()
61 ret = regmap_update_bits(pchip->regmap, REG_IO_CTRL, 0x7C, reg_val); in lm3639_chip_init()
76 reg_val = pdata->fled_pins; in lm3639_chip_init()
77 reg_val |= pdata->bled_pins; in lm3639_chip_init()
79 reg_val = pdata->fled_pins; in lm3639_chip_init()
80 reg_val |= pdata->bled_pins | 0x01; in lm3639_chip_init()
83 ret = regmap_update_bits(pchip->regmap, REG_ENABLE, 0x79, reg_val); in lm3639_chip_init()
97 unsigned int reg_val; in lm3639_bled_update_status() local
101 ret = regmap_read(pchip->regmap, REG_FLAG, ®_val); in lm3639_bled_update_status()
[all …]
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| /linux-6.1.9/sound/soc/amd/vangogh/ |
| D | acp5x-i2s.c | 93 u32 reg_val, frmt_reg; in acp5x_i2s_hwparams() local
131 reg_val = ACP_HSTDM_ITER; in acp5x_i2s_hwparams()
136 reg_val = ACP_I2STDM_ITER; in acp5x_i2s_hwparams()
142 reg_val = ACP_HSTDM_IRER; in acp5x_i2s_hwparams()
147 reg_val = ACP_I2STDM_IRER; in acp5x_i2s_hwparams()
152 val = acp_readl(rtd->acp5x_base + reg_val); in acp5x_i2s_hwparams()
153 acp_writel(val | 0x2, rtd->acp5x_base + reg_val); in acp5x_i2s_hwparams()
156 val = acp_readl(rtd->acp5x_base + reg_val); in acp5x_i2s_hwparams()
159 acp_writel(val, rtd->acp5x_base + reg_val); in acp5x_i2s_hwparams()
237 u32 ret, val, period_bytes, reg_val, ier_val, water_val; in acp5x_i2s_trigger() local
[all …]
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| /linux-6.1.9/drivers/gpu/drm/i915/gem/ |
| D | i915_gem_stolen.c | 193 u32 reg_val = intel_uncore_read(uncore, in g4x_get_stolen_reserved() local
200 IS_GM45(i915) ? "CTG" : "ELK", reg_val); in g4x_get_stolen_reserved()
202 if ((reg_val & G4X_STOLEN_RESERVED_ENABLE) == 0) in g4x_get_stolen_reserved()
211 reg_val); in g4x_get_stolen_reserved()
213 if (!(reg_val & G4X_STOLEN_RESERVED_ADDR2_MASK)) in g4x_get_stolen_reserved()
216 *base = (reg_val & G4X_STOLEN_RESERVED_ADDR2_MASK) << 16; in g4x_get_stolen_reserved()
218 (reg_val & G4X_STOLEN_RESERVED_ADDR1_MASK) < *base); in g4x_get_stolen_reserved()
228 u32 reg_val = intel_uncore_read(uncore, GEN6_STOLEN_RESERVED); in gen6_get_stolen_reserved() local
230 drm_dbg(&i915->drm, "GEN6_STOLEN_RESERVED = %08x\n", reg_val); in gen6_get_stolen_reserved()
232 if (!(reg_val & GEN6_STOLEN_RESERVED_ENABLE)) in gen6_get_stolen_reserved()
[all …]
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| /linux-6.1.9/drivers/mtd/nand/raw/ |
| D | omap_elm.c | 106 u32 reg_val; in elm_config() local
124 reg_val = (bch_type & ECC_BCH_LEVEL_MASK) | (ELM_ECC_SIZE << 16); in elm_config()
125 elm_write_reg(info, ELM_LOCATION_CONFIG, reg_val); in elm_config()
145 u32 reg_val; in elm_configure_page_mode() local
147 reg_val = elm_read_reg(info, ELM_PAGE_CTRL); in elm_configure_page_mode()
149 reg_val |= BIT(index); /* enable page mode */ in elm_configure_page_mode()
151 reg_val &= ~BIT(index); /* disable page mode */ in elm_configure_page_mode()
153 elm_write_reg(info, ELM_PAGE_CTRL, reg_val); in elm_configure_page_mode()
254 u32 reg_val; in elm_start_processing() local
264 reg_val = elm_read_reg(info, offset); in elm_start_processing()
[all …]
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dmub/src/ |
| D | dmub_reg.c | 76 uint32_t reg_val; in dmub_reg_update() local
84 reg_val = srv->funcs.reg_read(srv->user_ctx, addr); in dmub_reg_update()
85 reg_val = (reg_val & ~field_value_mask.mask) | field_value_mask.value; in dmub_reg_update()
86 srv->funcs.reg_write(srv->user_ctx, addr, reg_val); in dmub_reg_update()
89 void dmub_reg_set(struct dmub_srv *srv, uint32_t addr, uint32_t reg_val, int n, in dmub_reg_set() argument
100 reg_val = (reg_val & ~field_value_mask.mask) | field_value_mask.value; in dmub_reg_set()
101 srv->funcs.reg_write(srv->user_ctx, addr, reg_val); in dmub_reg_set()
107 uint32_t reg_val = srv->funcs.reg_read(srv->user_ctx, addr); in dmub_reg_get() local
108 *field_value = get_reg_field_value_ex(reg_val, mask, shift); in dmub_reg_get()
|
| /linux-6.1.9/drivers/edac/ |
| D | dmc520_edac.c | 255 u32 reg_val = readl(reg_base + REG_OFFSET_FEATURE_CONFIG); in dmc520_is_ecc_enabled() local
257 return FIELD_GET(REG_FIELD_DRAM_ECC_ENABLED, reg_val); in dmc520_is_ecc_enabled()
263 u32 reg_val, scrub_cfg; in dmc520_get_scrub_type() local
265 reg_val = dmc520_read_reg(pvt, REG_OFFSET_SCRUB_CONTROL0_NOW); in dmc520_get_scrub_type()
266 scrub_cfg = FIELD_GET(SCRUB_TRIGGER0_NEXT_MASK, reg_val); in dmc520_get_scrub_type()
280 u32 reg_val; in dmc520_get_memory_width() local
282 reg_val = dmc520_read_reg(pvt, REG_OFFSET_FORMAT_CONTROL); in dmc520_get_memory_width()
283 mem_width_field = FIELD_GET(MEMORY_WIDTH_MASK, reg_val); in dmc520_get_memory_width()
296 u32 reg_val; in dmc520_get_mtype() local
298 reg_val = dmc520_read_reg(pvt, REG_OFFSET_MEMORY_TYPE_NOW); in dmc520_get_mtype()
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| /linux-6.1.9/drivers/media/i2c/ |
| D | lm3646.c | 102 unsigned int reg_val; in lm3646_get_ctrl() local
108 rval = regmap_read(flash->regmap, REG_FLAG, ®_val); in lm3646_get_ctrl()
113 if (reg_val & FAULT_TIMEOUT) in lm3646_get_ctrl()
115 if (reg_val & FAULT_SHORT_CIRCUIT) in lm3646_get_ctrl()
117 if (reg_val & FAULT_UVLO) in lm3646_get_ctrl()
119 if (reg_val & FAULT_IVFM) in lm3646_get_ctrl()
121 if (reg_val & FAULT_OCP) in lm3646_get_ctrl()
123 if (reg_val & FAULT_OVERTEMP) in lm3646_get_ctrl()
125 if (reg_val & FAULT_NTC_TRIP) in lm3646_get_ctrl()
127 if (reg_val & FAULT_OVP) in lm3646_get_ctrl()
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