Home
last modified time | relevance | path

Searched refs:regVPG0_VPG_MEM_PWR_BASE_IDX (Results 1 – 6 of 6) sorted by relevance

/linux-6.1.9/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_3_1_2_offset.h11288 #define regVPG0_VPG_MEM_PWR_BASE_IDX … macro
Ddcn_3_1_4_offset.h9123 #define regVPG0_VPG_MEM_PWR_BASE_IDX … macro
Ddcn_3_1_5_offset.h11033 #define regVPG0_VPG_MEM_PWR_BASE_IDX … macro
Ddcn_3_2_0_offset.h10450 #define regVPG0_VPG_MEM_PWR_BASE_IDX … macro
Ddcn_3_2_1_offset.h10449 #define regVPG0_VPG_MEM_PWR_BASE_IDX … macro
Ddcn_3_1_6_offset.h11512 #define regVPG0_VPG_MEM_PWR_BASE_IDX … macro