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Searched refs:regSDMA1_QUEUE1_MIDCMD_DATA9_BASE_IDX (Results 1 – 2 of 2) sorted by relevance

/linux-6.1.9/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_11_0_0_offset.h1209 #define regSDMA1_QUEUE1_MIDCMD_DATA9_BASE_IDX … macro
Dgc_11_0_3_offset.h1221 #define regSDMA1_QUEUE1_MIDCMD_DATA9_BASE_IDX … macro