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Searched refs:regPWRSEQ1_BL_PWM_CNTL2 (Results 1 – 8 of 8) sorted by relevance

/linux-6.1.9/drivers/gpu/drm/amd/include/asic_reg/dpcs/
Ddpcs_3_1_4_offset.h7204 #define regPWRSEQ1_BL_PWM_CNTL2 … macro
Ddpcs_4_2_0_offset.h122 #define regPWRSEQ1_BL_PWM_CNTL2 … macro
Ddpcs_4_2_2_offset.h109 #define regPWRSEQ1_BL_PWM_CNTL2 … macro
Ddpcs_4_2_3_offset.h126 #define regPWRSEQ1_BL_PWM_CNTL2 … macro
/linux-6.1.9/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_3_1_2_offset.h12457 #define regPWRSEQ1_BL_PWM_CNTL2 … macro
Ddcn_3_1_4_offset.h11570 #define regPWRSEQ1_BL_PWM_CNTL2 … macro
Ddcn_3_1_5_offset.h12322 #define regPWRSEQ1_BL_PWM_CNTL2 … macro
Ddcn_3_1_6_offset.h13053 #define regPWRSEQ1_BL_PWM_CNTL2 … macro