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Searched refs:regPWRSEQ1_BL_PWM_CNTL (Results 1 – 8 of 8) sorted by relevance

/linux-6.1.9/drivers/gpu/drm/amd/include/asic_reg/dpcs/
Ddpcs_3_1_4_offset.h7202 #define regPWRSEQ1_BL_PWM_CNTL … macro
Ddpcs_4_2_0_offset.h120 #define regPWRSEQ1_BL_PWM_CNTL … macro
Ddpcs_4_2_2_offset.h107 #define regPWRSEQ1_BL_PWM_CNTL … macro
Ddpcs_4_2_3_offset.h124 #define regPWRSEQ1_BL_PWM_CNTL … macro
/linux-6.1.9/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_3_1_2_offset.h12455 #define regPWRSEQ1_BL_PWM_CNTL … macro
Ddcn_3_1_4_offset.h11568 #define regPWRSEQ1_BL_PWM_CNTL … macro
Ddcn_3_1_5_offset.h12320 #define regPWRSEQ1_BL_PWM_CNTL … macro
Ddcn_3_1_6_offset.h13051 #define regPWRSEQ1_BL_PWM_CNTL … macro