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Searched refs:regPWRSEQ0_PANEL_PWRSEQ_DELAY1_BASE_IDX (Results 1 – 8 of 8) sorted by relevance

/linux-6.1.9/drivers/gpu/drm/amd/include/asic_reg/dpcs/
Ddpcs_3_1_4_offset.h7163 #define regPWRSEQ0_PANEL_PWRSEQ_DELAY1_BASE_IDX … macro
Ddpcs_4_2_0_offset.h81 #define regPWRSEQ0_PANEL_PWRSEQ_DELAY1_BASE_IDX … macro
Ddpcs_4_2_2_offset.h68 #define regPWRSEQ0_PANEL_PWRSEQ_DELAY1_BASE_IDX … macro
Ddpcs_4_2_3_offset.h85 #define regPWRSEQ0_PANEL_PWRSEQ_DELAY1_BASE_IDX … macro
/linux-6.1.9/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_3_1_2_offset.h12416 #define regPWRSEQ0_PANEL_PWRSEQ_DELAY1_BASE_IDX … macro
Ddcn_3_1_4_offset.h11529 #define regPWRSEQ0_PANEL_PWRSEQ_DELAY1_BASE_IDX … macro
Ddcn_3_1_5_offset.h12281 #define regPWRSEQ0_PANEL_PWRSEQ_DELAY1_BASE_IDX … macro
Ddcn_3_1_6_offset.h13012 #define regPWRSEQ0_PANEL_PWRSEQ_DELAY1_BASE_IDX … macro