Home
last modified time | relevance | path

Searched refs:regMPCC0_MPCC_UPDATE_LOCK_SEL (Results 1 – 6 of 6) sorted by relevance

/linux-6.1.9/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_3_1_2_offset.h6463 #define regMPCC0_MPCC_UPDATE_LOCK_SEL … macro
Ddcn_3_1_4_offset.h13228 #define regMPCC0_MPCC_UPDATE_LOCK_SEL … macro
Ddcn_3_1_5_offset.h6222 #define regMPCC0_MPCC_UPDATE_LOCK_SEL … macro
Ddcn_3_2_0_offset.h4765 #define regMPCC0_MPCC_UPDATE_LOCK_SEL … macro
Ddcn_3_2_1_offset.h4764 #define regMPCC0_MPCC_UPDATE_LOCK_SEL … macro
Ddcn_3_1_6_offset.h6683 #define regMPCC0_MPCC_UPDATE_LOCK_SEL … macro