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Searched refs:regMPCC0_MPCC_SM_CONTROL_BASE_IDX (Results 1 – 6 of 6) sorted by relevance

/linux-6.1.9/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_3_1_2_offset.h6462 #define regMPCC0_MPCC_SM_CONTROL_BASE_IDX … macro
Ddcn_3_1_4_offset.h13227 #define regMPCC0_MPCC_SM_CONTROL_BASE_IDX … macro
Ddcn_3_1_5_offset.h6221 #define regMPCC0_MPCC_SM_CONTROL_BASE_IDX … macro
Ddcn_3_2_0_offset.h4764 #define regMPCC0_MPCC_SM_CONTROL_BASE_IDX … macro
Ddcn_3_2_1_offset.h4763 #define regMPCC0_MPCC_SM_CONTROL_BASE_IDX … macro
Ddcn_3_1_6_offset.h6682 #define regMPCC0_MPCC_SM_CONTROL_BASE_IDX … macro