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Searched refs:regDSCL1_DSCL_MEM_PWR_STATUS_BASE_IDX (Results 1 – 6 of 6) sorted by relevance

/linux-6.1.9/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_3_1_2_offset.h4518 #define regDSCL1_DSCL_MEM_PWR_STATUS_BASE_IDX … macro
Ddcn_3_1_4_offset.h5431 #define regDSCL1_DSCL_MEM_PWR_STATUS_BASE_IDX … macro
Ddcn_3_1_5_offset.h4277 #define regDSCL1_DSCL_MEM_PWR_STATUS_BASE_IDX … macro
Ddcn_3_2_0_offset.h3738 #define regDSCL1_DSCL_MEM_PWR_STATUS_BASE_IDX … macro
Ddcn_3_2_1_offset.h3737 #define regDSCL1_DSCL_MEM_PWR_STATUS_BASE_IDX … macro
Ddcn_3_1_6_offset.h4738 #define regDSCL1_DSCL_MEM_PWR_STATUS_BASE_IDX … macro