Home
last modified time | relevance | path

Searched refs:regDSCL0_DSCL_MEM_PWR_CTRL_BASE_IDX (Results 1 – 6 of 6) sorted by relevance

/linux-6.1.9/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_3_1_2_offset.h3824 #define regDSCL0_DSCL_MEM_PWR_CTRL_BASE_IDX … macro
Ddcn_3_1_4_offset.h4737 #define regDSCL0_DSCL_MEM_PWR_CTRL_BASE_IDX … macro
Ddcn_3_1_5_offset.h3583 #define regDSCL0_DSCL_MEM_PWR_CTRL_BASE_IDX … macro
Ddcn_3_2_0_offset.h3350 #define regDSCL0_DSCL_MEM_PWR_CTRL_BASE_IDX … macro
Ddcn_3_2_1_offset.h3349 #define regDSCL0_DSCL_MEM_PWR_CTRL_BASE_IDX … macro
Ddcn_3_1_6_offset.h4044 #define regDSCL0_DSCL_MEM_PWR_CTRL_BASE_IDX … macro