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Searched refs:regDCCG_VSYNC_OTG5_LATCH_VALUE (Results 1 – 6 of 6) sorted by relevance

/linux-6.1.9/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_3_1_2_offset.h401 #define regDCCG_VSYNC_OTG5_LATCH_VALUE … macro
Ddcn_3_1_4_offset.h1493 #define regDCCG_VSYNC_OTG5_LATCH_VALUE … macro
Ddcn_3_1_5_offset.h188 #define regDCCG_VSYNC_OTG5_LATCH_VALUE … macro
Ddcn_3_2_0_offset.h194 #define regDCCG_VSYNC_OTG5_LATCH_VALUE … macro
Ddcn_3_2_1_offset.h194 #define regDCCG_VSYNC_OTG5_LATCH_VALUE … macro
Ddcn_3_1_6_offset.h601 #define regDCCG_VSYNC_OTG5_LATCH_VALUE … macro