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Searched refs:regCP_ME_CNTL (Results 1 – 4 of 4) sorted by relevance

/linux-6.1.9/drivers/gpu/drm/amd/amdgpu/
Dgfx_v11_0.c2150 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); in gfx_v11_0_config_pfp_cache_rs64()
2157 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_config_pfp_cache_rs64()
2166 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_config_pfp_cache_rs64()
2273 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); in gfx_v11_0_config_me_cache_rs64()
2280 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_config_me_cache_rs64()
2289 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_config_me_cache_rs64()
2434 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); in gfx_v11_0_config_gfx_rs64()
2437 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_config_gfx_rs64()
2442 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_config_gfx_rs64()
2456 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); in gfx_v11_0_config_gfx_rs64()
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/linux-6.1.9/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_4_2_offset.h239 #define regCP_ME_CNTL … macro
Dgc_11_0_0_offset.h6198 #define regCP_ME_CNTL … macro
Dgc_11_0_3_offset.h6470 #define regCP_ME_CNTL … macro