Searched refs:regCP_CPC_IC_BASE_CNTL (Results 1 – 4 of 4) sorted by relevance
| /linux-6.1.9/drivers/gpu/drm/amd/amdgpu/ |
| D | gfx_v11_0.c | 2065 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); in gfx_v11_0_config_mec_cache()
2069 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); in gfx_v11_0_config_mec_cache()
2335 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); in gfx_v11_0_config_mec_cache_rs64()
2339 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); in gfx_v11_0_config_mec_cache_rs64()
3419 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); in gfx_v11_0_cp_compute_load_microcode_rs64()
3423 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); in gfx_v11_0_cp_compute_load_microcode_rs64()
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| /linux-6.1.9/drivers/gpu/drm/amd/include/asic_reg/gc/ |
| D | gc_9_4_2_offset.h | 585 #define regCP_CPC_IC_BASE_CNTL … macro
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| D | gc_11_0_0_offset.h | 9728 #define regCP_CPC_IC_BASE_CNTL … macro
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| D | gc_11_0_3_offset.h | 10282 #define regCP_CPC_IC_BASE_CNTL … macro
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