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Searched refs:regCM1_CM_POST_CSC_C31_C32_BASE_IDX (Results 1 – 6 of 6) sorted by relevance

/linux-6.1.9/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_3_1_2_offset.h4540 #define regCM1_CM_POST_CSC_C31_C32_BASE_IDX … macro
Ddcn_3_1_4_offset.h5453 #define regCM1_CM_POST_CSC_C31_C32_BASE_IDX … macro
Ddcn_3_1_5_offset.h4299 #define regCM1_CM_POST_CSC_C31_C32_BASE_IDX … macro
Ddcn_3_2_0_offset.h3760 #define regCM1_CM_POST_CSC_C31_C32_BASE_IDX … macro
Ddcn_3_2_1_offset.h3759 #define regCM1_CM_POST_CSC_C31_C32_BASE_IDX … macro
Ddcn_3_1_6_offset.h4760 #define regCM1_CM_POST_CSC_C31_C32_BASE_IDX … macro