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Searched refs:regCM0_CM_POST_CSC_C31_C32_BASE_IDX (Results 1 – 6 of 6) sorted by relevance

/linux-6.1.9/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_3_1_2_offset.h3848 #define regCM0_CM_POST_CSC_C31_C32_BASE_IDX … macro
Ddcn_3_1_4_offset.h4761 #define regCM0_CM_POST_CSC_C31_C32_BASE_IDX … macro
Ddcn_3_1_5_offset.h3607 #define regCM0_CM_POST_CSC_C31_C32_BASE_IDX … macro
Ddcn_3_2_0_offset.h3374 #define regCM0_CM_POST_CSC_C31_C32_BASE_IDX … macro
Ddcn_3_2_1_offset.h3373 #define regCM0_CM_POST_CSC_C31_C32_BASE_IDX … macro
Ddcn_3_1_6_offset.h4068 #define regCM0_CM_POST_CSC_C31_C32_BASE_IDX … macro