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Searched refs:read_csr (Results 1 – 17 of 17) sorted by relevance

/linux-6.1.9/drivers/infiniband/hw/hfi1/
Dfirmware.c244 while ((read_csr(dd, DC_DC8051_CFG_RAM_ACCESS_STATUS) in __read_8051_data()
256 *result = read_csr(dd, DC_DC8051_CFG_RAM_ACCESS_RD_DATA); in __read_8051_data()
329 while ((read_csr(dd, DC_DC8051_CFG_RAM_ACCESS_STATUS) in write_8051()
793 status = (read_csr(dd, MISC_CFG_FW_CTRL) in run_rsa()
828 status = (read_csr(dd, MISC_CFG_FW_CTRL) in run_rsa()
876 reg = read_csr(dd, MISC_ERR_STATUS); in run_rsa()
906 u64 reg = read_csr(dd, DC_DC8051_STS_CUR_STATE); in get_firmware_state()
1062 reg = read_csr(dd, ASIC_STS_SBUS_RESULT); in sbus_read()
1183 reg = read_csr(dd, ASIC_STS_SBUS_RESULT); in sbus_request_slow()
1187 u64 counts = read_csr(dd, ASIC_STS_SBUS_COUNTERS); in sbus_request_slow()
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Dintr.c140 read_csr(dd, DC_DC8051_STS_REMOTE_GUID); in handle_linkup_change()
142 read_csr(dd, DC_DC8051_STS_REMOTE_NODE_TYPE) & in handle_linkup_change()
145 read_csr(dd, DC_DC8051_STS_REMOTE_PORT_NO) & in handle_linkup_change()
148 read_csr(dd, DC_DC8051_STS_REMOTE_FM_SECURITY) & in handle_linkup_change()
Dchip.h575 u64 read_csr(const struct hfi1_devdata *dd, u32 offset);
587 return read_csr(dd, offset0 + (0x100 * ctxt)); in read_kctxt_csr()
622 return read_csr(dd, offset0 + (0x1000 * ctxt)); in read_uctxt_csr()
634 return read_csr(dd, RCV_CONTEXTS); in chip_rcv_contexts()
639 return read_csr(dd, SEND_CONTEXTS); in chip_send_contexts()
644 return read_csr(dd, SEND_DMA_ENGINES); in chip_sdma_engines()
649 return read_csr(dd, SEND_PIO_MEM_SIZE); in chip_pio_mem_size()
654 return read_csr(dd, SEND_DMA_MEM_SIZE); in chip_sdma_mem_size()
659 return read_csr(dd, RCV_ARRAY_CNT); in chip_rcv_array_count()
Dqsfp.c32 reg = read_csr(dd, target_oe); in hfi1_setsda()
45 (void)read_csr(dd, target_oe); in hfi1_setsda()
56 reg = read_csr(dd, target_oe); in hfi1_setscl()
69 (void)read_csr(dd, target_oe); in hfi1_setscl()
82 reg = read_csr(bus->controlling_dd, target_in); in hfi1_getsda()
96 reg = read_csr(bus->controlling_dd, target_in); in hfi1_getscl()
646 reg = read_csr(dd, dd->hfi1_id ? ASIC_QSFP2_IN : ASIC_QSFP1_IN); in qsfp_mod_present()
Dchip.c1308 u64 read_csr(const struct hfi1_devdata *dd, u32 offset) in read_csr() function
1356 ret = read_csr(dd, csr); in read_write_csr()
5227 mask = read_csr(rcd->dd, CCE_INT_MASK + (8 * (is / 64))); in is_urg_masked()
5678 u64 src = read_csr(dd, SEND_EGRESS_ERR_SOURCE); /* read first */ in handle_send_egress_err_info()
5679 u64 info = read_csr(dd, SEND_EGRESS_ERR_INFO); in handle_send_egress_err_info()
6341 reg = read_csr(dd, DC_DC8051_CFG_EXT_DEV_1); in handle_8051_request()
6369 (void)read_csr(dd, DCC_CFG_RESET); in handle_8051_request()
6396 u64 reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT); in set_up_vau()
6411 u64 reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT); in set_up_vl15()
6484 dd->lcb_err_en = read_csr(dd, DC_LCB_ERR_EN); in lcb_shutdown()
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Dpcie.c859 read_csr(dd, ASIC_PCIE_SD_HOST_CMD); in arm_gasket_logic()
889 pcie_ctrl = read_csr(dd, CCE_PCIE_CTRL); in write_xmt_margin()
1027 therm = read_csr(dd, ASIC_CFG_THERM_POLL_EN); in do_pcie_gen3_transition()
1256 (void)read_csr(dd, CCE_DC_CTRL); /* DC reset hold */ in do_pcie_gen3_transition()
1258 fw_ctrl = read_csr(dd, MISC_CFG_FW_CTRL); in do_pcie_gen3_transition()
1322 reg = read_csr(dd, ASIC_PCIE_SD_HOST_STATUS); in do_pcie_gen3_transition()
Dplatform.c19 temp_scratch = read_csr(dd, ASIC_CFG_SCRATCH); in validate_scratch_checksum()
38 temp_scratch = read_csr(dd, ASIC_CFG_SCRATCH + (8 * i)); in validate_scratch_checksum()
48 temp_scratch = read_csr(dd, ASIC_CFG_SCRATCH); in validate_scratch_checksum()
64 temp_scratch = read_csr(dd, ASIC_CFG_SCRATCH_1); in save_platform_config_fields()
94 temp_scratch = read_csr(dd, dd->hfi1_id ? ASIC_CFG_SCRATCH_3 : in save_platform_config_fields()
Dpio.c26 sendctrl = read_csr(dd, SEND_CTRL); in __cm_reset()
43 reg = read_csr(dd, SEND_CTRL); in pio_send_control()
83 (void)read_csr(dd, SEND_CTRL); /* flush write */ in pio_send_control()
978 reg = read_csr(dd, sc->hw_context * 8 + in sc_wait_for_packet_egress()
1201 reg = read_csr(dd, SEND_PIO_INIT_CTXT); in pio_init_wait_progress()
Deprom.c53 result[i] = (u32)read_csr(dd, ASIC_EEP_DATA); in read_page()
Ddebugfs.c520 scratch0 = read_csr(dd, ASIC_CFG_SCRATCH); in asic_flags_read()
577 scratch0 = read_csr(dd, ASIC_CFG_SCRATCH); in asic_flags_write()
581 (void)read_csr(dd, ASIC_CFG_SCRATCH); in asic_flags_write()
Dsdma.c274 reg = read_csr(dd, off + SEND_EGRESS_SEND_DMA_STATUS); in sdma_wait_for_packet_egress()
2046 csr = read_csr(sde->dd, reg); \
2057 csr = read_csr(sde->dd, reg + (8 * i)); \
Dmad.c1776 *val++ = read_csr(dd, SEND_SC2VLT0); in get_sc2vlt_tables()
1777 *val++ = read_csr(dd, SEND_SC2VLT1); in get_sc2vlt_tables()
1778 *val++ = read_csr(dd, SEND_SC2VLT2); in get_sc2vlt_tables()
1779 *val++ = read_csr(dd, SEND_SC2VLT3); in get_sc2vlt_tables()
3386 reg = read_csr(dd, RCV_ERR_INFO); in pma_get_opa_errorinfo()
/linux-6.1.9/drivers/net/ethernet/amd/
Dpcnet32.c242 u16 (*read_csr) (unsigned long, int); member
382 .read_csr = pcnet32_wio_read_csr,
437 .read_csr = pcnet32_dwio_read_csr,
462 val = lp->a->read_csr(ioaddr, CSR3); in pcnet32_netif_start()
689 csr5 = a->read_csr(ioaddr, CSR5); in pcnet32_suspend()
694 while (!(a->read_csr(ioaddr, CSR5) & CSR5_SUSPEND)) { in pcnet32_suspend()
713 int csr5 = lp->a->read_csr(ioaddr, CSR5); in pcnet32_clr_suspend()
773 csr15 = lp->a->read_csr(ioaddr, CSR15) & ~0x0180; in pcnet32_set_link_ksettings()
1053 x = a->read_csr(ioaddr, CSR15) & 0xfffc; in pcnet32_loopback_test()
1111 x = a->read_csr(ioaddr, CSR15); in pcnet32_loopback_test()
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/linux-6.1.9/drivers/firewire/
Dcore-card.c661 .read_csr = dummy_read_csr,
727 if (card->driver->read_csr == dummy_read_csr) in fw_card_read_cycle_time()
732 *cycle_time = card->driver->read_csr(card, CSR_CYCLE_TIME); in fw_card_read_cycle_time()
Dcore.h91 u32 (*read_csr)(struct fw_card *card, int csr_offset); member
Dcore-transaction.c1135 *data = cpu_to_be32(card->driver->read_csr(card, reg)); in handle_registers()
Dohci.c3505 .read_csr = ohci_read_csr,