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Searched refs:rd32 (Results 1 – 25 of 95) sorted by relevance

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/linux-6.1.9/drivers/net/ethernet/intel/igc/
Digc_mac.c27 ctrl = rd32(IGC_CTRL); in igc_disable_pcie_master()
32 if (!(rd32(IGC_STATUS) & in igc_disable_pcie_master()
181 ctrl = rd32(IGC_CTRL); in igc_force_mac_fc()
237 rd32(IGC_CRCERRS); in igc_clear_hw_cntrs_base()
238 rd32(IGC_MPC); in igc_clear_hw_cntrs_base()
239 rd32(IGC_SCC); in igc_clear_hw_cntrs_base()
240 rd32(IGC_ECOL); in igc_clear_hw_cntrs_base()
241 rd32(IGC_MCC); in igc_clear_hw_cntrs_base()
242 rd32(IGC_LATECOL); in igc_clear_hw_cntrs_base()
243 rd32(IGC_COLC); in igc_clear_hw_cntrs_base()
[all …]
Digc_i225.c48 swsm = rd32(IGC_SWSM); in igc_get_hw_semaphore_i225()
64 swsm = rd32(IGC_SWSM); in igc_get_hw_semaphore_i225()
81 swsm = rd32(IGC_SWSM); in igc_get_hw_semaphore_i225()
85 if (rd32(IGC_SWSM) & IGC_SWSM_SWESMBI) in igc_get_hw_semaphore_i225()
123 swfw_sync = rd32(IGC_SW_FW_SYNC); in igc_acquire_swfw_sync_i225()
169 swfw_sync = rd32(IGC_SW_FW_SYNC); in igc_release_swfw_sync_i225()
252 rd32(IGC_SRWR)) { in igc_write_nvm_srwr()
356 reg = rd32(IGC_EECD); in igc_pool_flash_update_done_i225()
382 flup = rd32(IGC_EECD) | IGC_EECD_FLUPD_I225; in igc_update_flash_i225()
463 eec = rd32(IGC_EECD); in igc_get_flash_presence_i225()
[all …]
Digc_base.c40 ctrl = rd32(IGC_CTRL); in igc_reset_hw_base()
56 rd32(IGC_ICR); in igc_reset_hw_base()
68 u32 eecd = rd32(IGC_EECD); in igc_init_nvm_params_base()
113 ctrl = rd32(IGC_CTRL); in igc_setup_copper_link_base()
165 hw->bus.func = (rd32(IGC_STATUS) & IGC_STATUS_FUNC_MASK) >> in igc_init_phy_params_base()
338 rfctl = rd32(IGC_RFCTL); in igc_rx_fifo_flush_base()
342 if (!(rd32(IGC_MANC) & IGC_MANC_RCV_TCO_EN)) in igc_rx_fifo_flush_base()
347 rxdctl[i] = rd32(IGC_RXDCTL(i)); in igc_rx_fifo_flush_base()
356 rx_enabled |= rd32(IGC_RXDCTL(i)); in igc_rx_fifo_flush_base()
370 rlpml = rd32(IGC_RLPML); in igc_rx_fifo_flush_base()
[all …]
Digc_dump.c54 regs[n] = rd32(IGC_RDLEN(n)); in igc_regdump()
58 regs[n] = rd32(IGC_RDH(n)); in igc_regdump()
62 regs[n] = rd32(IGC_RDT(n)); in igc_regdump()
66 regs[n] = rd32(IGC_RXDCTL(n)); in igc_regdump()
70 regs[n] = rd32(IGC_RDBAL(n)); in igc_regdump()
74 regs[n] = rd32(IGC_RDBAH(n)); in igc_regdump()
78 regs[n] = rd32(IGC_TDBAL(n)); in igc_regdump()
82 regs[n] = rd32(IGC_TDBAH(n)); in igc_regdump()
86 regs[n] = rd32(IGC_TDLEN(n)); in igc_regdump()
90 regs[n] = rd32(IGC_TDH(n)); in igc_regdump()
[all …]
Digc_ptp.c30 nsec = rd32(IGC_SYSTIML); in igc_ptp_read()
31 sec = rd32(IGC_SYSTIMH); in igc_ptp_read()
102 ts->tv_nsec = rd32(IGC_SYSTIML); in igc_ptp_gettimex64_i225()
103 ts->tv_sec = rd32(IGC_SYSTIMH); in igc_ptp_gettimex64_i225()
177 ctrl = rd32(IGC_CTRL); in igc_pin_perout()
178 ctrl_ext = rd32(IGC_CTRL_EXT); in igc_pin_perout()
179 tssdp = rd32(IGC_TSSDP); in igc_pin_perout()
223 ctrl = rd32(IGC_CTRL); in igc_pin_extts()
224 ctrl_ext = rd32(IGC_CTRL_EXT); in igc_pin_extts()
225 tssdp = rd32(IGC_TSSDP); in igc_pin_extts()
[all …]
Digc_nvm.c23 reg = rd32(IGC_EERD); in igc_poll_eerd_eewr_done()
25 reg = rd32(IGC_EEWR); in igc_poll_eerd_eewr_done()
49 u32 eecd = rd32(IGC_EECD); in igc_acquire_nvm()
53 eecd = rd32(IGC_EECD); in igc_acquire_nvm()
59 eecd = rd32(IGC_EECD); in igc_acquire_nvm()
83 eecd = rd32(IGC_EECD); in igc_release_nvm()
122 data[i] = (rd32(IGC_EERD) >> IGC_NVM_RW_REG_DATA); in igc_read_nvm_eerd()
139 rar_high = rd32(IGC_RAH(0)); in igc_read_mac_addr()
140 rar_low = rd32(IGC_RAL(0)); in igc_read_mac_addr()
Digc_ethtool.c179 regs_buff[0] = rd32(IGC_CTRL); in igc_ethtool_get_regs()
180 regs_buff[1] = rd32(IGC_STATUS); in igc_ethtool_get_regs()
181 regs_buff[2] = rd32(IGC_CTRL_EXT); in igc_ethtool_get_regs()
182 regs_buff[3] = rd32(IGC_MDIC); in igc_ethtool_get_regs()
183 regs_buff[4] = rd32(IGC_CONNSW); in igc_ethtool_get_regs()
186 regs_buff[5] = rd32(IGC_EECD); in igc_ethtool_get_regs()
192 regs_buff[6] = rd32(IGC_EICS); in igc_ethtool_get_regs()
193 regs_buff[7] = rd32(IGC_EICS); in igc_ethtool_get_regs()
194 regs_buff[8] = rd32(IGC_EIMS); in igc_ethtool_get_regs()
195 regs_buff[9] = rd32(IGC_EIMC); in igc_ethtool_get_regs()
[all …]
Digc_diag.c45 before = rd32(reg); in reg_pattern_test()
47 val = rd32(reg); in reg_pattern_test()
67 before = rd32(reg); in reg_set_and_check()
69 val = rd32(reg); in reg_set_and_check()
95 before = rd32(IGC_STATUS); in igc_reg_test()
98 after = rd32(IGC_STATUS) & toggle; in igc_reg_test()
Digc_tsn.c63 tqavctrl = rd32(IGC_TQAVCTRL); in igc_tsn_disable_offload()
97 tqavctrl = rd32(IGC_TQAVCTRL); in igc_tsn_enable_offload()
182 tqavcc = rd32(IGC_TQAVCC(i)); in igc_tsn_enable_offload()
194 tqavcc = rd32(IGC_TQAVCC(i)); in igc_tsn_enable_offload()
206 nsec = rd32(IGC_SYSTIML); in igc_tsn_enable_offload()
207 sec = rd32(IGC_SYSTIMH); in igc_tsn_enable_offload()
Digc_main.c159 ctrl_ext = rd32(IGC_CTRL_EXT); in igc_release_hw_control()
178 ctrl_ext = rd32(IGC_CTRL_EXT); in igc_get_hw_control()
768 rxcsum = rd32(IGC_RXCSUM); in igc_setup_mrqc()
805 rctl = rd32(IGC_RCTL); in igc_setup_rctl()
856 tctl = rd32(IGC_TCTL); in igc_setup_tctl()
1741 ctrl = rd32(IGC_CTRL); in igc_vlan_mode()
2945 !(rd32(IGC_STATUS) & IGC_STATUS_TXOFF)) { in igc_clean_tx_irq()
2960 rd32(IGC_TDH(tx_ring->reg_idx)), in igc_clean_tx_irq()
3008 ral = rd32(IGC_RAL(i)); in igc_find_mac_filter()
3009 rah = rd32(IGC_RAH(i)); in igc_find_mac_filter()
[all …]
Digc_phy.c18 manc = rd32(IGC_MANC); in igc_check_reset_block()
180 phpm = rd32(IGC_I225_PHPM); in igc_phy_hw_reset()
182 ctrl = rd32(IGC_CTRL); in igc_phy_hw_reset()
194 phpm = rd32(IGC_I225_PHPM); in igc_phy_hw_reset()
575 mdic = rd32(IGC_MDIC); in igc_read_phy_reg_mdic()
632 mdic = rd32(IGC_MDIC); in igc_write_phy_reg_mdic()
/linux-6.1.9/drivers/net/ethernet/intel/igb/
De1000_mac.c58 reg = rd32(E1000_STATUS); in igb_get_bus_info_pcie()
153 bits = rd32(E1000_VLVF(regindex)) & E1000_VLVF_VLANID_MASK; in igb_find_vlvf_slot()
224 bits = rd32(E1000_VLVF(vlvf_index)); in igb_vfta_set()
560 rd32(E1000_CRCERRS); in igb_clear_hw_cntrs_base()
561 rd32(E1000_SYMERRS); in igb_clear_hw_cntrs_base()
562 rd32(E1000_MPC); in igb_clear_hw_cntrs_base()
563 rd32(E1000_SCC); in igb_clear_hw_cntrs_base()
564 rd32(E1000_ECOL); in igb_clear_hw_cntrs_base()
565 rd32(E1000_MCC); in igb_clear_hw_cntrs_base()
566 rd32(E1000_LATECOL); in igb_clear_hw_cntrs_base()
[all …]
De1000_82575.c96 reg = rd32(E1000_MDIC); in igb_sgmii_uses_mdio_82575()
104 reg = rd32(E1000_MDICNFG); in igb_sgmii_uses_mdio_82575()
192 ctrl_ext = rd32(E1000_CTRL_EXT); in igb_init_phy_params_82575()
225 hw->bus.func = (rd32(E1000_STATUS) & E1000_STATUS_FUNC_MASK) >> in igb_init_phy_params_82575()
330 u32 eecd = rd32(E1000_EECD); in igb_init_nvm_params_82575()
453 (rd32(E1000_FWSM) & E1000_FWSM_MODE_MASK) in igb_init_mac_params_82575()
502 ctrl_ext = rd32(E1000_CTRL_EXT); in igb_set_sfp_media_type_82575()
627 ctrl_ext = rd32(E1000_CTRL_EXT); in igb_get_invariants_82575()
851 mdic = rd32(E1000_MDIC); in igb_get_phy_id_82575()
860 mdic = rd32(E1000_MDICNFG); in igb_get_phy_id_82575()
[all …]
Digb_ethtool.c147 0 : rd32(E1000_STATUS); in igb_get_link_ksettings()
477 regs_buff[0] = rd32(E1000_CTRL); in igb_get_regs()
478 regs_buff[1] = rd32(E1000_STATUS); in igb_get_regs()
479 regs_buff[2] = rd32(E1000_CTRL_EXT); in igb_get_regs()
480 regs_buff[3] = rd32(E1000_MDIC); in igb_get_regs()
481 regs_buff[4] = rd32(E1000_SCTL); in igb_get_regs()
482 regs_buff[5] = rd32(E1000_CONNSW); in igb_get_regs()
483 regs_buff[6] = rd32(E1000_VET); in igb_get_regs()
484 regs_buff[7] = rd32(E1000_LEDCTL); in igb_get_regs()
485 regs_buff[8] = rd32(E1000_PBA); in igb_get_regs()
[all …]
Digb_ptp.c82 lo = rd32(E1000_SYSTIML); in igb_ptp_read_82576()
83 hi = rd32(E1000_SYSTIMH); in igb_ptp_read_82576()
103 rd32(E1000_SYSTIMR); in igb_ptp_read_82580()
104 lo = rd32(E1000_SYSTIML); in igb_ptp_read_82580()
105 hi = rd32(E1000_SYSTIMH); in igb_ptp_read_82580()
124 rd32(E1000_SYSTIMR); in igb_ptp_read_i210()
125 nsec = rd32(E1000_SYSTIML); in igb_ptp_read_i210()
126 sec = rd32(E1000_SYSTIMH); in igb_ptp_read_i210()
292 lo = rd32(E1000_SYSTIML); in igb_ptp_gettimex_82576()
294 hi = rd32(E1000_SYSTIMH); in igb_ptp_gettimex_82576()
[all …]
De1000_i210.c30 swsm = rd32(E1000_SWSM); in igb_get_hw_semaphore_i210()
46 swsm = rd32(E1000_SWSM); in igb_get_hw_semaphore_i210()
63 swsm = rd32(E1000_SWSM); in igb_get_hw_semaphore_i210()
67 if (rd32(E1000_SWSM) & E1000_SWSM_SWESMBI) in igb_get_hw_semaphore_i210()
131 swfw_sync = rd32(E1000_SW_FW_SYNC); in igb_acquire_swfw_sync_i210()
170 swfw_sync = rd32(E1000_SW_FW_SYNC); in igb_release_swfw_sync_i210()
254 rd32(E1000_SRWR)) { in igb_write_nvm_srwr()
332 invm_dword = rd32(E1000_INVM_DATA_REG(i)); in igb_read_invm_word_i210()
458 invm_dword = rd32(E1000_INVM_DATA_REG(i)); in igb_read_invm_version()
634 reg = rd32(E1000_EECD); in igb_pool_flash_update_done_i210()
[all …]
Digb_main.c295 regs[n] = rd32(E1000_RDLEN(n)); in igb_regdump()
299 regs[n] = rd32(E1000_RDH(n)); in igb_regdump()
303 regs[n] = rd32(E1000_RDT(n)); in igb_regdump()
307 regs[n] = rd32(E1000_RXDCTL(n)); in igb_regdump()
311 regs[n] = rd32(E1000_RDBAL(n)); in igb_regdump()
315 regs[n] = rd32(E1000_RDBAH(n)); in igb_regdump()
319 regs[n] = rd32(E1000_TDBAL(n)); in igb_regdump()
323 regs[n] = rd32(E1000_TDBAH(n)); in igb_regdump()
327 regs[n] = rd32(E1000_TDLEN(n)); in igb_regdump()
331 regs[n] = rd32(E1000_TDH(n)); in igb_regdump()
[all …]
De1000_nvm.c53 u32 eecd = rd32(E1000_EECD); in igb_shift_out_eec_bits()
98 eecd = rd32(E1000_EECD); in igb_shift_in_eec_bits()
107 eecd = rd32(E1000_EECD); in igb_shift_in_eec_bits()
135 reg = rd32(E1000_EERD); in igb_poll_eerd_eewr_done()
137 reg = rd32(E1000_EEWR); in igb_poll_eerd_eewr_done()
160 u32 eecd = rd32(E1000_EECD); in igb_acquire_nvm()
166 eecd = rd32(E1000_EECD); in igb_acquire_nvm()
172 eecd = rd32(E1000_EECD); in igb_acquire_nvm()
195 u32 eecd = rd32(E1000_EECD); in igb_standby_nvm()
220 eecd = rd32(E1000_EECD); in e1000_stop_nvm()
[all …]
De1000_mbx.c244 u32 mbvficr = rd32(E1000_MBVFICR); in igb_check_for_bit_pf()
302 u32 vflre = rd32(E1000_VFLRE); in igb_check_for_rst_pf()
332 p2v_mailbox = rd32(E1000_P2VMAILBOX(vf_number)); in igb_obtain_mbx_lock_pf()
355 p2v_mailbox = rd32(E1000_P2VMAILBOX(vf_number)); in igb_release_mbx_lock_pf()
/linux-6.1.9/drivers/net/fjes/
Dfjes_ethtool.c194 regs_buff[0] = rd32(XSCT_OWNER_EPID); in fjes_get_regs()
195 regs_buff[1] = rd32(XSCT_MAX_EP); in fjes_get_regs()
198 regs_buff[4] = rd32(XSCT_DCTL); in fjes_get_regs()
201 regs_buff[8] = rd32(XSCT_CR); in fjes_get_regs()
202 regs_buff[9] = rd32(XSCT_CS); in fjes_get_regs()
203 regs_buff[10] = rd32(XSCT_SHSTSAL); in fjes_get_regs()
204 regs_buff[11] = rd32(XSCT_SHSTSAH); in fjes_get_regs()
206 regs_buff[13] = rd32(XSCT_REQBL); in fjes_get_regs()
207 regs_buff[14] = rd32(XSCT_REQBAL); in fjes_get_regs()
208 regs_buff[15] = rd32(XSCT_REQBAH); in fjes_get_regs()
[all …]
/linux-6.1.9/drivers/net/ethernet/intel/i40e/
Di40e_ptp.c162 lo = rd32(hw, I40E_PRTTSYN_EVNT_L(0)); in i40e_ptp_extts0_work()
163 hi = rd32(hw, I40E_PRTTSYN_EVNT_H(0)); in i40e_ptp_extts0_work()
231 rd32(&pf->hw, I40E_PRTTSYN_RXTIME_L(i)); in i40_ptp_reset_timing_events()
232 rd32(&pf->hw, I40E_PRTTSYN_RXTIME_H(i)); in i40_ptp_reset_timing_events()
236 rd32(&pf->hw, I40E_PRTTSYN_TXTIME_L); in i40_ptp_reset_timing_events()
237 rd32(&pf->hw, I40E_PRTTSYN_TXTIME_H); in i40_ptp_reset_timing_events()
289 lo = rd32(hw, I40E_PRTTSYN_TIME_L); in i40e_ptp_read()
291 hi = rd32(hw, I40E_PRTTSYN_TIME_H); in i40e_ptp_read()
651 prttsyn_stat = rd32(hw, I40E_PRTTSYN_STAT_1); in i40e_ptp_get_rx_events()
710 rd32(hw, I40E_PRTTSYN_RXTIME_H(i)); in i40e_ptp_rx_hang()
[all …]
Di40e_dcb.c22 reg = rd32(hw, I40E_PRTDCB_GENS); in i40e_get_dcbx_status()
1321 u32 reg = rd32(hw, I40E_PRTDCB_RETSC); in i40e_dcb_hw_rx_fifo_config()
1390 reg = rd32(hw, I40E_PRT_SWR_PM_THR); in i40e_dcb_hw_rx_cmd_monitor_config()
1396 reg = rd32(hw, I40E_PRTDCB_RPPMC); in i40e_dcb_hw_rx_cmd_monitor_config()
1435 reg = rd32(hw, I40E_PRTDCB_MFLCN); in i40e_dcb_hw_pfc_config()
1448 reg = rd32(hw, I40E_PRTDCB_FCCFG); in i40e_dcb_hw_pfc_config()
1459 reg = rd32(hw, I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GPP); in i40e_dcb_hw_pfc_config()
1463 reg = rd32(hw, I40E_PRTMAC_HSEC_CTL_RX_ENABLE_PPP); in i40e_dcb_hw_pfc_config()
1469 reg = rd32(hw, I40E_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE); in i40e_dcb_hw_pfc_config()
1476 reg = rd32(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE); in i40e_dcb_hw_pfc_config()
[all …]
Di40e_diag.c22 orig_val = rd32(hw, reg); in i40e_diag_reg_pattern_test()
26 val = rd32(hw, reg); in i40e_diag_reg_pattern_test()
36 val = rd32(hw, reg); in i40e_diag_reg_pattern_test()
/linux-6.1.9/drivers/gpu/drm/nouveau/nvkm/core/
Dgpuobj.c76 .rd32 = nvkm_gpuobj_rd32_fast,
84 .rd32 = nvkm_gpuobj_heap_rd32,
139 .rd32 = nvkm_gpuobj_rd32_fast,
147 .rd32 = nvkm_gpuobj_rd32,
/linux-6.1.9/drivers/net/ethernet/intel/ice/
Dice_osdep.h22 #define rd32(a, reg) readl((a)->hw_addr + (reg)) macro
26 #define ice_flush(a) rd32((a), GLGEN_STAT)

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