| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/ |
| D | dm_pp_smu.h | 48 struct pp_smu { struct
97 struct pp_smu pp_smu; member
103 void (*set_display_count)(struct pp_smu *pp, int count);
112 void (*set_wm_ranges)(struct pp_smu *pp,
118 void (*set_hard_min_dcfclk_by_freq)(struct pp_smu *pp, int mhz);
124 void (*set_min_deep_sleep_dcfclk)(struct pp_smu *pp, int mhz);
129 void (*set_hard_min_fclk_by_freq)(struct pp_smu *pp, int mhz);
134 void (*set_hard_min_socclk_by_freq)(struct pp_smu *pp, int mhz);
137 void (*set_pme_wa_enable)(struct pp_smu *pp);
168 struct pp_smu pp_smu; member
[all …]
|
| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/ |
| D | rv1_clk_mgr.c | 198 struct pp_smu_funcs_rv *pp_smu = NULL; in rv1_update_clocks() local
205 ASSERT(clk_mgr->pp_smu); in rv1_update_clocks()
210 pp_smu = &clk_mgr->pp_smu->rv_funcs; in rv1_update_clocks()
223 if (pp_smu->set_display_count) in rv1_update_clocks()
224 pp_smu->set_display_count(&pp_smu->pp_smu, display_count); in rv1_update_clocks()
264 if (pp_smu->set_hard_min_fclk_by_freq && in rv1_update_clocks()
265 pp_smu->set_hard_min_dcfclk_by_freq && in rv1_update_clocks()
266 pp_smu->set_min_deep_sleep_dcfclk) { in rv1_update_clocks()
267 pp_smu->set_hard_min_fclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(new_clocks->fclk_khz)); in rv1_update_clocks()
268 pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(new_clocks->dcfclk_khz)); in rv1_update_clocks()
[all …]
|
| D | rv2_clk_mgr.c | 37 …gr_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_mgr, struct pp_smu_funcs *pp_smu) in rv2_clk_mgr_construct() argument
40 rv1_clk_mgr_construct(ctx, clk_mgr, pp_smu); in rv2_clk_mgr_construct()
|
| D | rv1_clk_mgr.h | 29 …r_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_mgr, struct pp_smu_funcs *pp_smu);
|
| D | rv2_clk_mgr.h | 29 …r_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_mgr, struct pp_smu_funcs *pp_smu);
|
| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/ |
| D | dcn20_clk_mgr.c | 223 struct pp_smu_funcs_nv *pp_smu = NULL; in dcn2_update_clocks() local
247 if (dc->res_pool->pp_smu) in dcn2_update_clocks()
248 pp_smu = &dc->res_pool->pp_smu->nv_funcs; in dcn2_update_clocks()
254 if (pp_smu && pp_smu->set_display_count) in dcn2_update_clocks()
255 pp_smu->set_display_count(&pp_smu->pp_smu, display_count); in dcn2_update_clocks()
264 if (pp_smu && pp_smu->set_hard_min_dcfclk_by_freq) in dcn2_update_clocks()
265 …pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_khz… in dcn2_update_clocks()
271 if (pp_smu && pp_smu->set_min_deep_sleep_dcfclk) in dcn2_update_clocks()
272 …pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_deep_… in dcn2_update_clocks()
277 if (pp_smu && pp_smu->set_hard_min_socclk_by_freq) in dcn2_update_clocks()
[all …]
|
| D | dcn20_clk_mgr.h | 43 struct pp_smu_funcs *pp_smu,
|
| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/clk_mgr/ |
| D | clk_mgr.c | 147 struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *pp_smu, struct dccg … in dc_clk_mgr_create() argument
233 rn_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
238 rn_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
242 rv2_clk_mgr_construct(ctx, clk_mgr, pp_smu); in dc_clk_mgr_create()
247 rv1_clk_mgr_construct(ctx, clk_mgr, pp_smu); in dc_clk_mgr_create()
260 dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
264 dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
268 dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
272 dcn201_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
275 dcn20_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
[all …]
|
| /linux-6.1.9/drivers/gpu/drm/amd/display/amdgpu_dm/ |
| D | amdgpu_dm_pp_smu.c | 463 static void pp_rv_set_wm_ranges(struct pp_smu *pp, in pp_rv_set_wm_ranges()
512 static void pp_rv_set_pme_wa_enable(struct pp_smu *pp) in pp_rv_set_pme_wa_enable()
520 static void pp_rv_set_active_display_count(struct pp_smu *pp, int count) in pp_rv_set_active_display_count()
528 static void pp_rv_set_min_deep_sleep_dcfclk(struct pp_smu *pp, int clock) in pp_rv_set_min_deep_sleep_dcfclk()
536 static void pp_rv_set_hard_min_dcefclk_by_freq(struct pp_smu *pp, int clock) in pp_rv_set_hard_min_dcefclk_by_freq()
544 static void pp_rv_set_hard_min_fclk_by_freq(struct pp_smu *pp, int mhz) in pp_rv_set_hard_min_fclk_by_freq()
552 static enum pp_smu_status pp_nv_set_wm_ranges(struct pp_smu *pp, in pp_nv_set_wm_ranges()
563 static enum pp_smu_status pp_nv_set_display_count(struct pp_smu *pp, int count) in pp_nv_set_display_count()
580 pp_nv_set_min_deep_sleep_dcfclk(struct pp_smu *pp, int mhz) in pp_nv_set_min_deep_sleep_dcfclk()
597 struct pp_smu *pp, int mhz) in pp_nv_set_hard_min_dcefclk_by_freq()
[all …]
|
| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/ |
| D | rn_clk_mgr.c | 515 struct pp_smu_funcs *pp_smu = clk_mgr->pp_smu; in rn_notify_wm_ranges() local
521 if (pp_smu && pp_smu->rn_funcs.set_wm_ranges) in rn_notify_wm_ranges()
522 pp_smu->rn_funcs.set_wm_ranges(&pp_smu->rn_funcs.pp_smu, &clk_mgr_base->ranges); in rn_notify_wm_ranges()
701 struct pp_smu_funcs *pp_smu, in rn_clk_mgr_construct() argument
716 clk_mgr->pp_smu = pp_smu; in rn_clk_mgr_construct()
777 if (pp_smu && pp_smu->rn_funcs.get_dpm_clock_table) { in rn_clk_mgr_construct()
778 status = pp_smu->rn_funcs.get_dpm_clock_table(&pp_smu->rn_funcs.pp_smu, &clock_table); in rn_clk_mgr_construct()
|
| D | rn_clk_mgr.h | 46 struct pp_smu_funcs *pp_smu,
|
| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn21/ |
| D | dcn21_resource.c | 483 static void dcn21_pp_smu_destroy(struct pp_smu_funcs **pp_smu);
804 if (pool->base.pp_smu != NULL) in dcn21_resource_destruct()
805 dcn21_pp_smu_destroy(&pool->base.pp_smu); in dcn21_resource_destruct()
1139 struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL); in dcn21_pp_smu_create() local
1141 if (!pp_smu) in dcn21_pp_smu_create()
1142 return pp_smu; in dcn21_pp_smu_create()
1144 dm_pp_get_funcs(ctx, pp_smu); in dcn21_pp_smu_create()
1146 if (pp_smu->ctx.ver != PP_SMU_VER_RN) in dcn21_pp_smu_create()
1147 pp_smu = memset(pp_smu, 0, sizeof(struct pp_smu_funcs)); in dcn21_pp_smu_create()
1150 return pp_smu; in dcn21_pp_smu_create()
[all …]
|
| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn20/ |
| D | dcn20_resource.c | 1071 static void dcn20_pp_smu_destroy(struct pp_smu_funcs **pp_smu);
1206 if (pool->base.pp_smu != NULL) in dcn20_resource_destruct()
1207 dcn20_pp_smu_destroy(&pool->base.pp_smu); in dcn20_resource_destruct()
2281 struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_ATOMIC); in dcn20_pp_smu_create() local
2283 if (!pp_smu) in dcn20_pp_smu_create()
2284 return pp_smu; in dcn20_pp_smu_create()
2286 dm_pp_get_funcs(ctx, pp_smu); in dcn20_pp_smu_create()
2288 if (pp_smu->ctx.ver != PP_SMU_VER_NV) in dcn20_pp_smu_create()
2289 pp_smu = memset(pp_smu, 0, sizeof(struct pp_smu_funcs)); in dcn20_pp_smu_create()
2291 return pp_smu; in dcn20_pp_smu_create()
[all …]
|
| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/ |
| D | dcn201_clk_mgr.h | 31 struct pp_smu_funcs *pp_smu,
|
| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/ |
| D | dcn32_clk_mgr.h | 32 struct pp_smu_funcs *pp_smu,
|
| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/ |
| D | dcn315_clk_mgr.h | 44 struct pp_smu_funcs *pp_smu,
|
| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/ |
| D | dcn316_clk_mgr.h | 44 struct pp_smu_funcs *pp_smu,
|
| D | dcn316_clk_mgr.c | 616 struct pp_smu_funcs *pp_smu, in dcn316_clk_mgr_construct() argument
624 clk_mgr->base.pp_smu = pp_smu; in dcn316_clk_mgr_construct()
|
| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/ |
| D | vg_clk_mgr.h | 47 struct pp_smu_funcs *pp_smu,
|
| D | vg_clk_mgr.c | 646 struct pp_smu_funcs *pp_smu, in vg_clk_mgr_construct() argument
654 clk_mgr->base.pp_smu = pp_smu; in vg_clk_mgr_construct()
|
| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/ |
| D | dcn314_clk_mgr.h | 52 struct pp_smu_funcs *pp_smu,
|
| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/ |
| D | dcn31_clk_mgr.h | 51 struct pp_smu_funcs *pp_smu,
|
| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn10/ |
| D | dcn10_resource.c | 906 struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL); in dcn10_pp_smu_create() local
908 if (!pp_smu) in dcn10_pp_smu_create()
909 return pp_smu; in dcn10_pp_smu_create()
911 dm_pp_get_funcs(ctx, pp_smu); in dcn10_pp_smu_create()
912 return pp_smu; in dcn10_pp_smu_create()
991 kfree(pool->base.pp_smu); in dcn10_resource_destruct()
1534 pool->base.pp_smu = dcn10_pp_smu_create(ctx); in dcn10_resource_construct()
1540 if (pool->base.pp_smu != NULL in dcn10_resource_construct()
1541 && pool->base.pp_smu->rv_funcs.set_pme_wa_enable != NULL) in dcn10_resource_construct()
|
| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/ |
| D | dcn30_clk_mgr.h | 93 struct pp_smu_funcs *pp_smu,
|
| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn301/ |
| D | dcn301_resource.c | 1344 struct pp_smu_funcs *pp_smu, in set_wm_ranges() argument
1384 pp_smu->nv_funcs.set_wm_ranges(&pp_smu->nv_funcs.pp_smu, &ranges); in set_wm_ranges()
1569 if (!dc->debug.disable_pplib_wm_range && pool->base.pp_smu->nv_funcs.set_wm_ranges) in dcn301_resource_construct()
1570 set_wm_ranges(pool->base.pp_smu, &dcn3_01_soc); in dcn301_resource_construct()
|