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Searched refs:post_div_val (Results 1 – 17 of 17) sorted by relevance

/linux-6.1.9/drivers/clk/qcom/
Dclk-pll.h69 u32 post_div_val; member
Dclk-alpha-pll.h127 u32 post_div_val; member
Dclk-cpu-8996.c113 .post_div_val = 0x1 << 8,
215 .post_div_val = 0x1 << 8,
Dlcc-ipq806x.c53 .post_div_val = 0x0,
Dclk-pll.c230 val |= config->post_div_val; in clk_pll_configure()
Dmmcc-msm8974.c2352 .post_div_val = 0x0,
2366 .post_div_val = 0x0,
Dclk-alpha-pll.c330 val |= config->post_div_val; in clk_alpha_pll_configure()
1123 val = config->post_div_val; in clk_fabia_pll_configure()
Dmmcc-apq8084.c3037 .post_div_val = 0x0,
3051 .post_div_val = 0x0,
Dgcc-qcm2290.c309 .post_div_val = 0x1 << 8,
360 .post_div_val = 0x1 << 8,
Dgcc-sm6115.c362 .post_div_val = 0x1 << 8,
412 .post_div_val = 0x1 << 8,
Dgcc-ipq8074.c4436 .post_div_val = 0x0,
4448 .post_div_val = 0x1 << 8,
Dgcc-msm8939.c217 .post_div_val = 0x0,
264 .post_div_val = 0x0,
Dgcc-ipq6018.c4161 .post_div_val = 0x0,
4173 .post_div_val = 0x1 << 8,
Dgcc-qcs404.c359 .post_div_val = 0x1 << 8,
Dmmcc-msm8960.c88 .post_div_val = 0x0,
Dgcc-msm8976.c165 .post_div_val = 0x0,
Dgcc-msm8953.c122 .post_div_val = BIT(8),