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Searched refs:pll1_div (Results 1 – 5 of 5) sorted by relevance

/linux-6.1.9/arch/sh/kernel/cpu/sh2a/
Dclock-sh7264.c26 static unsigned int pll1_div; variable
43 unsigned long rate = clk->parent->rate / pll1_div; in pll_recalc()
139 pll1_div = 3; in arch_clk_init()
141 pll1_div = 4; in arch_clk_init()
143 pll1_div = 1; in arch_clk_init()
/linux-6.1.9/drivers/clk/renesas/
Drcar-gen4-cpg.h55 u8 pll1_div; member
Drcar-gen3-cpg.h72 u8 pll1_div; member
Drcar-gen4-cpg.c205 div = cpg_pll_config->pll1_div; in rcar_gen4_cpg_clk_register()
Drcar-gen3-cpg.c364 div = cpg_pll_config->pll1_div; in rcar_gen3_cpg_clk_register()