| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| D | dcn20_fpu.c | 881 display_e2e_pipe_params_st *pipes) in dcn20_populate_dml_writeback_from_context() argument
894 pipes[pipe_cnt].dout.wb_enable = (wb_info->wb_enabled == true) ? 1 : 0; in dcn20_populate_dml_writeback_from_context()
895 pipes[pipe_cnt].dout.num_active_wb++; in dcn20_populate_dml_writeback_from_context()
896 pipes[pipe_cnt].dout.wb.wb_src_height = wb_info->dwb_params.cnv_params.crop_height; in dcn20_populate_dml_writeback_from_context()
897 pipes[pipe_cnt].dout.wb.wb_src_width = wb_info->dwb_params.cnv_params.crop_width; in dcn20_populate_dml_writeback_from_context()
898 pipes[pipe_cnt].dout.wb.wb_dst_width = wb_info->dwb_params.dest_width; in dcn20_populate_dml_writeback_from_context()
899 pipes[pipe_cnt].dout.wb.wb_dst_height = wb_info->dwb_params.dest_height; in dcn20_populate_dml_writeback_from_context()
900 pipes[pipe_cnt].dout.wb.wb_htaps_luma = 1; in dcn20_populate_dml_writeback_from_context()
901 pipes[pipe_cnt].dout.wb.wb_vtaps_luma = 1; in dcn20_populate_dml_writeback_from_context()
902 pipes[pipe_cnt].dout.wb.wb_htaps_chroma = wb_info->dwb_params.scaler_taps.h_taps_c; in dcn20_populate_dml_writeback_from_context()
[all …]
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| D | dcn20_fpu.h | 33 display_e2e_pipe_params_st *pipes);
37 display_e2e_pipe_params_st *pipes,
41 display_e2e_pipe_params_st *pipes,
46 display_e2e_pipe_params_st *pipes,
50 display_e2e_pipe_params_st *pipes,
78 display_e2e_pipe_params_st *pipes,
89 display_e2e_pipe_params_st *pipes);
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| D | dcn30_fpu.c | 258 struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes) in dcn30_fpu_populate_dml_writeback_from_context() argument
275 pipes[pipe_cnt].dout.wb_enable = 0; in dcn30_fpu_populate_dml_writeback_from_context()
276 pipes[pipe_cnt].dout.num_active_wb = 0; in dcn30_fpu_populate_dml_writeback_from_context()
282 pipes[pipe_cnt].dout.wb_enable = 1; in dcn30_fpu_populate_dml_writeback_from_context()
283 pipes[pipe_cnt].dout.num_active_wb++; in dcn30_fpu_populate_dml_writeback_from_context()
326 pipes[pipe_cnt].pipe.dest.pixel_rate_mhz, in dcn30_fpu_populate_dml_writeback_from_context()
333 pipes[pipe_cnt].pipe.dest.htotal, in dcn30_fpu_populate_dml_writeback_from_context()
338 pipes[pipe_cnt].dout.wb = dout_wb; in dcn30_fpu_populate_dml_writeback_from_context()
349 display_e2e_pipe_params_st *pipes, in dcn30_fpu_set_mcif_arb_params() argument
358 wb_arb_params->cli_watermark[i] = get_wm_writeback_urgent(dml, pipes, pipe_cnt) * 1000; in dcn30_fpu_set_mcif_arb_params()
[all …]
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| D | dcn30_fpu.h | 36 struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes);
40 display_e2e_pipe_params_st *pipes,
48 display_e2e_pipe_params_st *pipes,
68 display_e2e_pipe_params_st *pipes,
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dml/dcn301/ |
| D | dcn301_fpu.c | 296 display_e2e_pipe_params_st *pipes, in calculate_wm_set_for_vlevel() argument
303 pipes[0].clks_cfg.voltage = vlevel; in calculate_wm_set_for_vlevel()
304 pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz; in calculate_wm_set_for_vlevel()
305 pipes[0].clks_cfg.socclk_mhz = dml->soc.clock_limits[vlevel].socclk_mhz; in calculate_wm_set_for_vlevel()
311 wm_set->urgent_ns = get_wm_urgent(dml, pipes, pipe_cnt) * 1000; in calculate_wm_set_for_vlevel()
312 …wm_set->cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(dml, pipes, pipe_cnt) … in calculate_wm_set_for_vlevel()
313 wm_set->cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(dml, pipes, pipe_cnt) * 1000; in calculate_wm_set_for_vlevel()
314 wm_set->cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(dml, pipes, pipe_cnt) * 1000; in calculate_wm_set_for_vlevel()
315 wm_set->pte_meta_urgent_ns = get_wm_memory_trip(dml, pipes, pipe_cnt) * 1000; in calculate_wm_set_for_vlevel()
316 wm_set->frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(dml, pipes, pipe_cnt) * 1000; in calculate_wm_set_for_vlevel()
[all …]
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dml/dcn314/ |
| D | dcn314_fpu.c | 284 display_e2e_pipe_params_st *pipes, in dcn314_populate_dml_pipes_from_context_fpu() argument
294 dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate); in dcn314_populate_dml_pipes_from_context_fpu()
306 pipes[pipe_cnt].pipe.dest.vtotal = pipe->stream->adjust.v_total_min; in dcn314_populate_dml_pipes_from_context_fpu()
318 pipes[pipe_cnt].pipe.src.immediate_flip = true; in dcn314_populate_dml_pipes_from_context_fpu()
320 pipes[pipe_cnt].pipe.src.unbounded_req_mode = false; in dcn314_populate_dml_pipes_from_context_fpu()
321 pipes[pipe_cnt].pipe.src.hostvm = dc->res_pool->hubbub->riommu_active; in dcn314_populate_dml_pipes_from_context_fpu()
322 pipes[pipe_cnt].pipe.src.gpuvm = true; in dcn314_populate_dml_pipes_from_context_fpu()
323 pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_luma = 0; in dcn314_populate_dml_pipes_from_context_fpu()
324 pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_chroma = 0; in dcn314_populate_dml_pipes_from_context_fpu()
325 pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch; in dcn314_populate_dml_pipes_from_context_fpu()
[all …]
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| D | dcn32_fpu.h | 36 display_e2e_pipe_params_st *pipes,
50 display_e2e_pipe_params_st *pipes,
56 display_e2e_pipe_params_st *pipes,
62 display_e2e_pipe_params_st *pipes,
70 display_e2e_pipe_params_st *pipes,
76 void dcn32_zero_pipe_dcc_fraction(display_e2e_pipe_params_st *pipes,
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| D | dcn32_fpu.c | 254 display_e2e_pipe_params_st *pipes, in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch() argument
267 dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, false); in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
304 display_e2e_pipe_params_st *pipes, in dcn32_helper_populate_phantom_dlg_params() argument
318 pipes[pipe_idx].pipe.dest.vstartup_start = in dcn32_helper_populate_phantom_dlg_params()
319 get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); in dcn32_helper_populate_phantom_dlg_params()
320 pipes[pipe_idx].pipe.dest.vupdate_offset = in dcn32_helper_populate_phantom_dlg_params()
321 get_vupdate_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); in dcn32_helper_populate_phantom_dlg_params()
322 pipes[pipe_idx].pipe.dest.vupdate_width = in dcn32_helper_populate_phantom_dlg_params()
323 get_vupdate_width(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); in dcn32_helper_populate_phantom_dlg_params()
324 pipes[pipe_idx].pipe.dest.vready_offset = in dcn32_helper_populate_phantom_dlg_params()
[all …]
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn30/ |
| D | dcn30_resource.h | 51 display_e2e_pipe_params_st *pipes,
64 display_e2e_pipe_params_st *pipes,
70 display_e2e_pipe_params_st *pipes,
75 struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes);
79 display_e2e_pipe_params_st *pipes,
105 display_e2e_pipe_params_st *pipes, int pipe_cnt, int vlevel);
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| D | dcn31_fpu.c | 443 void dcn31_zero_pipe_dcc_fraction(display_e2e_pipe_params_st *pipes, in dcn31_zero_pipe_dcc_fraction() argument
448 pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_luma = 0; in dcn31_zero_pipe_dcc_fraction()
449 pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_chroma = 0; in dcn31_zero_pipe_dcc_fraction()
482 display_e2e_pipe_params_st *pipes, in dcn31_calculate_wm_and_dlg_fp() argument
503 pipes[0].clks_cfg.voltage = vlevel; in dcn31_calculate_wm_and_dlg_fp()
504 pipes[0].clks_cfg.dcfclk_mhz = dcfclk; in dcn31_calculate_wm_and_dlg_fp()
505 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz; in dcn31_calculate_wm_and_dlg_fp()
513 …context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cn… in dcn31_calculate_wm_and_dlg_fp()
514 …state_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; in dcn31_calculate_wm_and_dlg_fp()
515 …a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; in dcn31_calculate_wm_and_dlg_fp()
[all …]
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| D | dcn31_fpu.h | 34 void dcn31_zero_pipe_dcc_fraction(display_e2e_pipe_params_st *pipes,
42 display_e2e_pipe_params_st *pipes,
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| /linux-6.1.9/sound/sparc/ |
| D | dbri.c | 312 struct dbri_pipe pipes[DBRI_NO_PIPES]; /* DBRI's 32 data pipes */ member
769 dbri->pipes[n].desc = dbri->pipes[n].first_desc = -1; in dbri_initialize()
813 return ((pipe >= 0) && (dbri->pipes[pipe].desc != -1)); in pipe_active()
833 sdp = dbri->pipes[pipe].sdp; in reset_pipe()
846 desc = dbri->pipes[pipe].first_desc; in reset_pipe()
852 } while (desc != -1 && desc != dbri->pipes[pipe].first_desc); in reset_pipe()
854 dbri->pipes[pipe].desc = -1; in reset_pipe()
855 dbri->pipes[pipe].first_desc = -1; in reset_pipe()
882 dbri->pipes[pipe].sdp = sdp; in setup_pipe()
883 dbri->pipes[pipe].desc = -1; in setup_pipe()
[all …]
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| /linux-6.1.9/drivers/platform/goldfish/ |
| D | goldfish_pipe.c | 198 struct goldfish_pipe **pipes; member
522 pipe = dev->pipes[id]; in signalled_pipes_add_locked()
654 if (!dev->pipes[id]) in get_free_pipe_id_locked()
663 struct goldfish_pipe **pipes = in get_free_pipe_id_locked() local
664 kcalloc(new_capacity, sizeof(*pipes), GFP_ATOMIC); in get_free_pipe_id_locked()
665 if (!pipes) in get_free_pipe_id_locked()
667 memcpy(pipes, dev->pipes, sizeof(*pipes) * dev->pipes_capacity); in get_free_pipe_id_locked()
668 kfree(dev->pipes); in get_free_pipe_id_locked()
669 dev->pipes = pipes; in get_free_pipe_id_locked()
732 dev->pipes[id] = pipe; in goldfish_pipe_open()
[all …]
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dml/ |
| D | display_mode_vba.c | 46 const display_e2e_pipe_params_st *pipes,
54 const display_e2e_pipe_params_st *pipes, in dml_get_voltage_level() argument
60 || memcmp(pipes, mode_lib->vba.cache_pipes, in dml_get_voltage_level()
65 memcpy(mode_lib->vba.cache_pipes, pipes, sizeof(*pipes) * num_pipes); in dml_get_voltage_level()
68 if (need_recalculate && pipes[0].clks_cfg.dppclk_mhz != 0) in dml_get_voltage_level()
82 …attr(struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *pipes, unsigned int num_…
84 recalculate_params(mode_lib, pipes, num_pipes); \
130 …attr(struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *pipes, unsigned int num_…
133 recalculate_params(mode_lib, pipes, num_pipes); \
208 const display_e2e_pipe_params_st *pipes, in get_total_immediate_flip_bytes() argument
[all …]
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| D | display_mode_lib.c | 163 display_e2e_pipe_params_st *pipes, in dml_log_pipe_params() argument
175 pipe_src = &(pipes[i].pipe.src); in dml_log_pipe_params()
176 pipe_dest = &(pipes[i].pipe.dest); in dml_log_pipe_params()
177 scale_ratio_depth = &(pipes[i].pipe.scale_ratio_depth); in dml_log_pipe_params()
178 scale_taps = &(pipes[i].pipe.scale_taps); in dml_log_pipe_params()
179 dout = &(pipes[i].dout); in dml_log_pipe_params()
180 clks_cfg = &(pipes[i].clks_cfg); in dml_log_pipe_params()
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn31/ |
| D | dcn31_resource.h | 45 display_e2e_pipe_params_st *pipes,
50 display_e2e_pipe_params_st *pipes,
55 display_e2e_pipe_params_st *pipes);
59 display_e2e_pipe_params_st *pipes,
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| /linux-6.1.9/drivers/gpu/drm/arm/display/komeda/ |
| D | komeda_event.c | 110 return (a->pipes[0] | a->pipes[1]) & in is_new_frame()
120 u64 evts_mask = evts->global | evts->pipes[0] | evts->pipes[1]; in komeda_print_events()
147 evt_str(&str, evts->pipes[0]); in komeda_print_events()
149 evt_str(&str, evts->pipes[1]); in komeda_print_events()
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| /linux-6.1.9/drivers/gpu/drm/tidss/ |
| D | tidss_kms.c | 126 struct pipe pipes[TIDSS_MAX_PORTS]; in tidss_dispc_modeset_init() local
184 pipes[num_pipes].hw_videoport = i; in tidss_dispc_modeset_init()
185 pipes[num_pipes].bridge = bridge; in tidss_dispc_modeset_init()
186 pipes[num_pipes].enc_type = enc_type; in tidss_dispc_modeset_init()
212 tcrtc = tidss_crtc_create(tidss, pipes[i].hw_videoport, in tidss_dispc_modeset_init()
221 enc = tidss_encoder_create(tidss, pipes[i].enc_type, in tidss_dispc_modeset_init()
228 ret = drm_bridge_attach(enc, pipes[i].bridge, NULL, 0); in tidss_dispc_modeset_init()
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| /linux-6.1.9/Documentation/gpu/amdgpu/display/ |
| D | mpo-overview.rst | 50 For this hardware example, we have 4 pipes (if you don't know what AMD pipe
53 configuration for optimal single display output (e.g., 2 pipes per plane).
56 display - will see 4 pipes in use, 2 per plane.
204 the two displays, we need to use 2 pipes. See the example below where we avoid
207 - 1 display (1 pipe) + MPO (1 pipe), we will use two pipes
208 - 2 displays (2 pipes) + MPO (1-2 pipes); we will use 4 pipes. MPO in the
209 middle of both displays needs 2 pipes.
210 - 3 Displays (3 pipes) + MPO (1-2 pipes), we need 5 pipes.
217 * When ASIC has 3 pipes, AMD hardware can NOT support 2 displays with MPO
218 * When ASIC has 4 pipes, AMD hardware can NOT support 3 displays with MPO
[all …]
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn32/ |
| D | dcn32_resource_helpers.c | 282 display_e2e_pipe_params_st *pipes) in dcn32_determine_det_override() argument
340 pipes[pipe_cnt].pipe.src.det_size_override = pipe_segments[i] * DCN3_2_DET_SEG_SIZE; in dcn32_determine_det_override()
345 pipes[i].pipe.src.det_size_override = 4 * DCN3_2_DET_SEG_SIZE; //DCN3_2_DEFAULT_DET_SIZE in dcn32_determine_det_override()
350 display_e2e_pipe_params_st *pipes) in dcn32_set_det_allocations() argument
370 pipes[0].pipe.src.det_size_override = DCN3_2_MAX_DET_SIZE; in dcn32_set_det_allocations()
373 pipes[0].pipe.src.det_size_override = DCN3_2_DEFAULT_DET_SIZE; in dcn32_set_det_allocations()
374 pipes[0].pipe.src.unbounded_req_mode = true; in dcn32_set_det_allocations()
377 pipes[0].pipe.src.det_size_override = 320; // 5K or higher in dcn32_set_det_allocations()
381 dcn32_determine_det_override(dc, context, pipes); in dcn32_set_det_allocations()
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| D | dcn32_resource.c | 1695 display_e2e_pipe_params_st *pipes, in dcn32_enable_phantom_stream() argument
1715 …dcn32_set_phantom_stream_timing(dc, context, ref_pipe, phantom_stream, pipes, pipe_cnt, dc_pipe_id… in dcn32_enable_phantom_stream()
1767 display_e2e_pipe_params_st *pipes, in dcn32_add_phantom_pipes() argument
1777 phantom_stream = dcn32_enable_phantom_stream(dc, context, pipes, pipe_cnt, index); in dcn32_add_phantom_pipes()
1807 …display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_par… in dcn32_validate_bandwidth() local
1835 out = dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate); in dcn32_validate_bandwidth()
1854 dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel); in dcn32_validate_bandwidth()
1868 kfree(pipes); in dcn32_validate_bandwidth()
1877 display_e2e_pipe_params_st *pipes, in dcn32_populate_dml_pipes_from_context() argument
1887 dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate); in dcn32_populate_dml_pipes_from_context()
[all …]
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| /linux-6.1.9/drivers/gpu/drm/omapdrm/ |
| D | omap_drv.c | 309 struct omap_drm_pipeline *pipe = &priv->pipes[i]; in omap_disconnect_pipelines()
339 pipe = &priv->pipes[priv->num_pipes++]; in omap_connect_pipelines()
342 if (priv->num_pipes == ARRAY_SIZE(priv->pipes)) { in omap_connect_pipelines()
452 struct omap_drm_pipeline *pipe = &priv->pipes[i]; in omap_modeset_init()
472 sort(priv->pipes, priv->num_pipes, sizeof(priv->pipes[0]), in omap_modeset_init()
480 struct omap_drm_pipeline *pipe = &priv->pipes[i]; in omap_modeset_init()
491 struct omap_drm_pipeline *pipe = &priv->pipes[i]; in omap_modeset_init()
557 struct drm_connector *connector = priv->pipes[i].connector; in omap_modeset_enable_external_hpd()
562 if (priv->pipes[i].output->bridge) in omap_modeset_enable_external_hpd()
576 struct drm_connector *connector = priv->pipes[i].connector; in omap_modeset_disable_external_hpd()
[all …]
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| /linux-6.1.9/drivers/gpu/drm/arm/display/komeda/d71/ |
| D | d71_dev.c | 189 evts->pipes[0] |= KOMEDA_EVENT_FLIP; in d71_irq_handler()
191 evts->pipes[1] |= KOMEDA_EVENT_FLIP; in d71_irq_handler()
205 evts->pipes[0] |= get_pipeline_event(d71->pipes[0], gcu_status); in d71_irq_handler()
208 evts->pipes[1] |= get_pipeline_event(d71->pipes[1], gcu_status); in d71_irq_handler()
228 pipe = d71->pipes[i]; in d71_enable_irq()
247 pipe = d71->pipes[i]; in d71_disable_irq()
261 struct d71_pipeline *pipe = d71->pipes[master_pipe]; in d71_on_off_vblank()
435 d71->pipes[i] = to_d71_pipeline(pipe); in d71_enum_resources()
578 malidp_write32_mask(d71->pipes[i]->lpu_addr, LPU_TBU_CONTROL, in d71_connect_iommu()
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| /linux-6.1.9/net/nfc/nci/ |
| D | hci.c | 115 hdev->pipes[i].gate = NCI_HCI_INVALID_GATE; in nci_hci_reset_pipes()
116 hdev->pipes[i].host = NCI_HCI_INVALID_HOST; in nci_hci_reset_pipes()
126 if (ndev->hci_dev->pipes[i].host == host) { in nci_hci_reset_pipes_per_host()
127 ndev->hci_dev->pipes[i].gate = NCI_HCI_INVALID_GATE; in nci_hci_reset_pipes_per_host()
128 ndev->hci_dev->pipes[i].host = NCI_HCI_INVALID_HOST; in nci_hci_reset_pipes_per_host()
283 u8 gate = ndev->hci_dev->pipes[pipe].gate; in nci_hci_cmd_received()
312 ndev->hci_dev->pipes[new_pipe].gate = dest_gate; in nci_hci_cmd_received()
313 ndev->hci_dev->pipes[new_pipe].host = in nci_hci_cmd_received()
334 ndev->hci_dev->pipes[delete_info->pipe].gate = in nci_hci_cmd_received()
336 ndev->hci_dev->pipes[delete_info->pipe].host = in nci_hci_cmd_received()
[all …]
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| /linux-6.1.9/drivers/net/wireless/ath/ath6kl/ |
| D | usb.c | 70 struct ath6kl_usb_pipe pipes[ATH6KL_USB_PIPE_MAX]; member
255 ath6kl_usb_free_pipe_resources(&ar_usb->pipes[i]); in ath6kl_usb_cleanup_pipe_resources()
358 pipe = &ar_usb->pipes[pipe_num]; in ath6kl_usb_setup_pipe_resources()
474 if (ar_usb->pipes[i].ar_usb != NULL) in ath6kl_usb_flush_all()
475 usb_kill_anchored_urbs(&ar_usb->pipes[i].urb_submitted); in ath6kl_usb_flush_all()
496 ar_usb->pipes[ATH6KL_USB_PIPE_RX_DATA].urb_cnt_thresh = 1; in ath6kl_usb_start_recv_pipes()
498 ath6kl_usb_post_recv_transfers(&ar_usb->pipes[ATH6KL_USB_PIPE_RX_DATA], in ath6kl_usb_start_recv_pipes()
652 pipe = &ar_usb->pipes[i]; in ath6kl_usb_create()
708 device->pipes[i].urb_cnt_thresh = in hif_start()
709 device->pipes[i].urb_alloc / 2; in hif_start()
[all …]
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