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/linux-6.1.9/drivers/staging/media/atomisp/pci/runtime/pipeline/src/
Dpipeline.c44 struct ia_css_pipeline *pipeline,
53 static void ia_css_pipeline_set_zoom_stage(struct ia_css_pipeline *pipeline);
66 struct ia_css_pipeline *pipeline, in ia_css_pipeline_create() argument
71 assert(pipeline); in ia_css_pipeline_create()
73 pipeline, pipe_id, pipe_num, dvs_frame_delay); in ia_css_pipeline_create()
74 if (!pipeline) { in ia_css_pipeline_create()
79 pipeline_init_defaults(pipeline, pipe_id, pipe_num, dvs_frame_delay); in ia_css_pipeline_create()
108 void ia_css_pipeline_destroy(struct ia_css_pipeline *pipeline) in ia_css_pipeline_destroy() argument
110 assert(pipeline); in ia_css_pipeline_destroy()
111 IA_CSS_ENTER_PRIVATE("pipeline = %p", pipeline); in ia_css_pipeline_destroy()
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/linux-6.1.9/drivers/gpu/drm/xen/
Dxen_drm_front_kms.c93 static void send_pending_event(struct xen_drm_front_drm_pipeline *pipeline) in send_pending_event() argument
95 struct drm_crtc *crtc = &pipeline->pipe.crtc; in send_pending_event()
100 if (pipeline->pending_event) in send_pending_event()
101 drm_crtc_send_vblank_event(crtc, pipeline->pending_event); in send_pending_event()
102 pipeline->pending_event = NULL; in send_pending_event()
110 struct xen_drm_front_drm_pipeline *pipeline = in display_enable() local
119 ret = xen_drm_front_mode_set(pipeline, crtc->x, crtc->y, in display_enable()
126 pipeline->conn_connected = false; in display_enable()
134 struct xen_drm_front_drm_pipeline *pipeline = in display_disable() local
139 ret = xen_drm_front_mode_set(pipeline, 0, 0, 0, 0, 0, in display_disable()
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Dxen_drm_front_conn.c50 struct xen_drm_front_drm_pipeline *pipeline = in connector_detect() local
54 pipeline->conn_connected = false; in connector_detect()
56 return pipeline->conn_connected ? connector_status_connected : in connector_detect()
64 struct xen_drm_front_drm_pipeline *pipeline = in connector_get_modes() local
75 videomode.hactive = pipeline->width; in connector_get_modes()
76 videomode.vactive = pipeline->height; in connector_get_modes()
105 struct xen_drm_front_drm_pipeline *pipeline = in xen_drm_front_conn_init() local
110 pipeline->conn_connected = true; in xen_drm_front_conn_init()
/linux-6.1.9/drivers/isdn/mISDN/
Ddsp_pipeline.c159 int dsp_pipeline_init(struct dsp_pipeline *pipeline) in dsp_pipeline_init() argument
161 if (!pipeline) in dsp_pipeline_init()
164 INIT_LIST_HEAD(&pipeline->list); in dsp_pipeline_init()
169 static inline void _dsp_pipeline_destroy(struct dsp_pipeline *pipeline) in _dsp_pipeline_destroy() argument
173 list_for_each_entry_safe(entry, n, &pipeline->list, list) { in _dsp_pipeline_destroy()
176 dsp_hwec_disable(container_of(pipeline, struct dsp, in _dsp_pipeline_destroy()
177 pipeline)); in _dsp_pipeline_destroy()
184 void dsp_pipeline_destroy(struct dsp_pipeline *pipeline) in dsp_pipeline_destroy() argument
187 if (!pipeline) in dsp_pipeline_destroy()
190 _dsp_pipeline_destroy(pipeline); in dsp_pipeline_destroy()
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Ddsp.h236 pipeline; member
271 extern int dsp_pipeline_init(struct dsp_pipeline *pipeline);
272 extern void dsp_pipeline_destroy(struct dsp_pipeline *pipeline);
273 extern int dsp_pipeline_build(struct dsp_pipeline *pipeline, const char *cfg);
274 extern void dsp_pipeline_process_tx(struct dsp_pipeline *pipeline, u8 *data,
276 extern void dsp_pipeline_process_rx(struct dsp_pipeline *pipeline, u8 *data,
/linux-6.1.9/drivers/staging/media/atomisp/pci/runtime/pipeline/interface/
Dia_css_pipeline.h104 struct ia_css_pipeline *pipeline,
115 void ia_css_pipeline_destroy(struct ia_css_pipeline *pipeline);
125 struct ia_css_pipeline *pipeline);
133 int ia_css_pipeline_request_stop(struct ia_css_pipeline *pipeline);
149 void ia_css_pipeline_clean(struct ia_css_pipeline *pipeline);
163 struct ia_css_pipeline *pipeline,
174 void ia_css_pipeline_finalize_stages(struct ia_css_pipeline *pipeline,
183 int ia_css_pipeline_get_stage(struct ia_css_pipeline *pipeline,
197 *pipeline,
211 *pipeline,
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/linux-6.1.9/drivers/gpu/drm/msm/disp/mdp5/
Dmdp5_crtc.c94 struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline; in crtc_flush() local
101 return mdp5_ctl_commit(ctl, pipeline, flush_mask, start); in crtc_flush()
126 mixer = mdp5_cstate->pipeline.mixer; in crtc_flush_all()
129 r_mixer = mdp5_cstate->pipeline.r_mixer; in crtc_flush_all()
140 struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline; in complete_flip() local
158 mdp5_ctl_blend(ctl, pipeline, NULL, NULL, 0, 0); in complete_flip()
217 struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline; in blend_setup() local
222 struct mdp5_hw_mixer *mixer = pipeline->mixer; in blend_setup()
224 struct mdp5_hw_mixer *r_mixer = pipeline->r_mixer; in blend_setup()
358 mdp5_ctl_blend(ctl, pipeline, stage, r_stage, plane_cnt, in blend_setup()
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Dmdp5_ctl.c135 static void set_ctl_op(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline) in set_ctl_op() argument
138 struct mdp5_interface *intf = pipeline->intf; in set_ctl_op()
159 if (pipeline->r_mixer) in set_ctl_op()
168 int mdp5_ctl_set_pipeline(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline) in mdp5_ctl_set_pipeline() argument
171 struct mdp5_interface *intf = pipeline->intf; in mdp5_ctl_set_pipeline()
177 set_ctl_op(ctl, pipeline); in mdp5_ctl_set_pipeline()
183 struct mdp5_pipeline *pipeline) in start_signal_needed() argument
185 struct mdp5_interface *intf = pipeline->intf; in start_signal_needed()
227 struct mdp5_pipeline *pipeline, in mdp5_ctl_set_encoder_state() argument
230 struct mdp5_interface *intf = pipeline->intf; in mdp5_ctl_set_encoder_state()
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Dmdp5_cmd_encoder.c129 struct mdp5_pipeline *pipeline = mdp5_crtc_get_pipeline(encoder->crtc); in mdp5_cmd_encoder_disable() local
136 mdp5_ctl_set_encoder_state(ctl, pipeline, false); in mdp5_cmd_encoder_disable()
137 mdp5_ctl_commit(ctl, pipeline, mdp_ctl_flush_mask_encoder(intf), true); in mdp5_cmd_encoder_disable()
147 struct mdp5_pipeline *pipeline = mdp5_crtc_get_pipeline(encoder->crtc); in mdp5_cmd_encoder_enable() local
155 mdp5_ctl_commit(ctl, pipeline, mdp_ctl_flush_mask_encoder(intf), true); in mdp5_cmd_encoder_enable()
157 mdp5_ctl_set_encoder_state(ctl, pipeline, true); in mdp5_cmd_encoder_enable()
Dmdp5_ctl.h37 int mdp5_ctl_set_cursor(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline,
55 int mdp5_ctl_blend(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline,
72 u32 mdp5_ctl_commit(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline,
Dmdp5_encoder.c136 struct mdp5_pipeline *pipeline = mdp5_crtc_get_pipeline(encoder->crtc); in mdp5_vid_encoder_disable() local
145 mdp5_ctl_set_encoder_state(ctl, pipeline, false); in mdp5_vid_encoder_disable()
150 mdp5_ctl_commit(ctl, pipeline, mdp_ctl_flush_mask_encoder(intf), true); in mdp5_vid_encoder_disable()
171 struct mdp5_pipeline *pipeline = mdp5_crtc_get_pipeline(encoder->crtc); in mdp5_vid_encoder_enable() local
181 mdp5_ctl_commit(ctl, pipeline, mdp_ctl_flush_mask_encoder(intf), true); in mdp5_vid_encoder_enable()
183 mdp5_ctl_set_encoder_state(ctl, pipeline, true); in mdp5_vid_encoder_enable()
237 mdp5_cstate->pipeline.intf = intf; in mdp5_encoder_atomic_check()
/linux-6.1.9/drivers/net/wireless/ti/wl18xx/
Ddebugfs.c143 WL18XX_DEBUGFS_FWSTATS_FILE(pipeline, hs_tx_stat_fifo_int, "%u");
144 WL18XX_DEBUGFS_FWSTATS_FILE(pipeline, enc_tx_stat_fifo_int, "%u");
145 WL18XX_DEBUGFS_FWSTATS_FILE(pipeline, enc_rx_stat_fifo_int, "%u");
146 WL18XX_DEBUGFS_FWSTATS_FILE(pipeline, rx_complete_stat_fifo_int, "%u");
147 WL18XX_DEBUGFS_FWSTATS_FILE(pipeline, pre_proc_swi, "%u");
148 WL18XX_DEBUGFS_FWSTATS_FILE(pipeline, post_proc_swi, "%u");
149 WL18XX_DEBUGFS_FWSTATS_FILE(pipeline, sec_frag_swi, "%u");
150 WL18XX_DEBUGFS_FWSTATS_FILE(pipeline, pre_to_defrag_swi, "%u");
151 WL18XX_DEBUGFS_FWSTATS_FILE(pipeline, defrag_to_rx_xfer_swi, "%u");
152 WL18XX_DEBUGFS_FWSTATS_FILE(pipeline, dec_packet_in, "%u");
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/linux-6.1.9/Documentation/gpu/
Dkomeda-kms.rst15 architecture. A display pipeline is made up of multiple individual and
16 functional pipeline stages called components, and every component has some
17 specific capabilities that can give the flowed pipeline pixel data a
24 Layer is the first pipeline stage, which prepares the pixel data for the next
58 Final stage of display pipeline, Timing controller is not for the pixel
94 Single pipeline data flow
98 :alt: Single pipeline digraph
99 :caption: Single pipeline data flow
140 Dual pipeline with Slave enabled
144 :alt: Slave pipeline digraph
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/linux-6.1.9/sound/soc/sof/
Dipc4-pcm.c43 struct sof_ipc4_pipeline *pipeline; in sof_ipc4_trigger_pipelines() local
77 pipeline = (struct sof_ipc4_pipeline *)pipeline_widget->private; in sof_ipc4_trigger_pipelines()
79 if (pipeline->state == state) in sof_ipc4_trigger_pipelines()
83 if (pipeline->state != SOF_IPC4_PIPE_PAUSED) { in sof_ipc4_trigger_pipelines()
93 pipeline->state = SOF_IPC4_PIPE_PAUSED; in sof_ipc4_trigger_pipelines()
95 if (pipeline->state == state) in sof_ipc4_trigger_pipelines()
106 pipeline->state = state; in sof_ipc4_trigger_pipelines()
Dipc4-topology.c607 struct sof_ipc4_pipeline *pipeline; in sof_ipc4_widget_setup_comp_pipeline() local
610 pipeline = kzalloc(sizeof(*pipeline), GFP_KERNEL); in sof_ipc4_widget_setup_comp_pipeline()
611 if (!pipeline) in sof_ipc4_widget_setup_comp_pipeline()
614 ret = sof_update_ipc_object(scomp, pipeline, SOF_SCHED_TOKENS, swidget->tuples, in sof_ipc4_widget_setup_comp_pipeline()
615 swidget->num_tuples, sizeof(*pipeline), 1); in sof_ipc4_widget_setup_comp_pipeline()
630 pipeline->priority = 0; in sof_ipc4_widget_setup_comp_pipeline()
634 pipeline->priority, pipeline->lp_mode); in sof_ipc4_widget_setup_comp_pipeline()
636 swidget->private = pipeline; in sof_ipc4_widget_setup_comp_pipeline()
638 pipeline->msg.primary = SOF_IPC4_GLB_PIPE_PRIORITY(pipeline->priority); in sof_ipc4_widget_setup_comp_pipeline()
639 pipeline->msg.primary |= SOF_IPC4_GLB_PIPE_INSTANCE_ID(swidget->pipeline_id); in sof_ipc4_widget_setup_comp_pipeline()
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/linux-6.1.9/drivers/staging/media/atomisp/pci/runtime/binary/src/
Dbinary.c82 + info->pipeline.left_cropping + binary_dvs_env.width; in ia_css_binary_internal_res()
84 + info->pipeline.top_cropping + binary_dvs_env.height; in ia_css_binary_internal_res()
103 info->pipeline.left_cropping, info->pipeline.mode, in ia_css_binary_internal_res()
104 info->pipeline.c_subsampling, in ia_css_binary_internal_res()
105 info->output.num_chunks, info->pipeline.pipelining); in ia_css_binary_internal_res()
107 info->pipeline.top_cropping, in ia_css_binary_internal_res()
197 if (need_bds_factor_2_00 && binary->info->sp.pipeline.left_cropping > 0) in ia_css_binary_compute_shading_table_bayer_origin()
420 metrics->mode = info->pipeline.mode; in binary_init_metrics()
516 binary->next = binary_infos[binary->sp.pipeline.mode]; in ia_css_binary_init_infos()
517 binary_infos[binary->sp.pipeline.mode] = binary; in ia_css_binary_init_infos()
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/linux-6.1.9/Documentation/devicetree/bindings/display/
Darm,komeda.yaml15 to a 4K resolution each. Each pipeline can be composed of up to four
59 '^pipeline@[01]$':
90 - pipeline@0
107 dp0_pipe0: pipeline@0 {
119 dp0_pipe1: pipeline@1 {
Dallwinner,sun4i-a10-display-engine.yaml14 The display engine pipeline (and its entry point, since it can be
18 The Allwinner A10 Display pipeline is composed of several components
22 display pipeline, when there are multiple components of the same
35 For a two pipeline system such as the one depicted above, the lines
/linux-6.1.9/tools/testing/selftests/kvm/lib/
Dassert.c33 const char *pipeline = "|cat -n 1>&2"; in test_dump_stack() local
34 char cmd[strlen(addr2line) + strlen(pipeline) + in test_dump_stack()
57 c += sprintf(c, "%s", pipeline); in test_dump_stack()
/linux-6.1.9/sound/soc/intel/avs/
Dtopology.c1131 struct avs_tplg_pipeline *pipeline; in avs_tplg_pipeline_create() local
1135 pipeline = devm_kzalloc(comp->card->dev, sizeof(*pipeline), GFP_KERNEL); in avs_tplg_pipeline_create()
1136 if (!pipeline) in avs_tplg_pipeline_create()
1139 pipeline->owner = owner; in avs_tplg_pipeline_create()
1140 INIT_LIST_HEAD(&pipeline->mod_list); in avs_tplg_pipeline_create()
1151 ret = avs_parse_tokens(comp, pipeline, pipeline_parsers, in avs_tplg_pipeline_create()
1167 if (pipeline->num_bindings) in avs_tplg_pipeline_create()
1172 pipeline->bindings = devm_kcalloc(comp->card->dev, pipeline->num_bindings, in avs_tplg_pipeline_create()
1173 sizeof(*pipeline->bindings), GFP_KERNEL); in avs_tplg_pipeline_create()
1174 if (!pipeline->bindings) in avs_tplg_pipeline_create()
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/linux-6.1.9/Documentation/devicetree/bindings/arm/mstar/
Dmstar,l3bridge.yaml14 MStar/SigmaStar's Armv7 SoCs have a pipeline in the interface
16 devices are allowed to run the pipeline must be flushed to ensure
23 are and install a barrier that triggers the required pipeline flush.
/linux-6.1.9/Documentation/gpu/amdgpu/display/
Ddcn-overview.rst6 (DCN) works, we need to start with an overview of the hardware pipeline. Below
53 pipeline is connected to the Scalable Data Port (SDP) via DCHUB; you can see
86 Display pipeline can be broken down into two components that are usually
130 When discussing graphics on Linux, the **pipeline** term can sometimes be
132 when we say **pipeline**. In the DCN driver, we use the term **hardware
133 pipeline** or **pipeline** or just **pipe** as an abstraction to indicate a
135 core treats DCN blocks as individual resources, meaning we can build a pipeline
136 by taking resources for all individual hardware blocks to compose one pipeline.
139 arbitrarily assigned as needed. We have this pipeline concept for trying to
146 this log can help us to see part of this pipeline behavior in real-time::
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/linux-6.1.9/drivers/staging/media/atomisp/pci/
Dsh_css_param_shading.c265 left_cropping = (binary->info->sp.pipeline.left_cropping == 0) ? in prepare_shading_table()
271 left_padding = (left_padding + binary->info->sp.pipeline.left_cropping) * in prepare_shading_table()
273 binary->info->sp.pipeline.left_cropping; in prepare_shading_table()
277 top_padding = binary->info->sp.pipeline.top_cropping * bds_numerator / in prepare_shading_table()
279 binary->info->sp.pipeline.top_cropping; in prepare_shading_table()
/linux-6.1.9/drivers/staging/media/atomisp/
Dnotes.txt5 pipeline. It does not have its own memory, but instead uses main memory.
14 The actual processing pipeline is made by loading one or more programs,
25 So in this case a single binary handles the entire pipeline.
29 on the ISP can do multiple processing steps in a single pipeline
/linux-6.1.9/sound/soc/sof/intel/
Dhda-dai.c485 struct sof_ipc4_pipeline *pipeline = pipe_widget->private; in ipc4_hda_dai_trigger() local
492 pipeline->state = SOF_IPC4_PIPE_PAUSED; in ipc4_hda_dai_trigger()
501 pipeline->state = SOF_IPC4_PIPE_RESET; in ipc4_hda_dai_trigger()
513 struct sof_ipc4_pipeline *pipeline = pipe_widget->private; in ipc4_hda_dai_trigger() local
520 pipeline->state = SOF_IPC4_PIPE_PAUSED; in ipc4_hda_dai_trigger()
714 struct sof_ipc4_pipeline *pipeline; in ipc4_be_dai_common_trigger() local
723 pipeline = pipe_widget->private; in ipc4_be_dai_common_trigger()
733 pipeline->state = SOF_IPC4_PIPE_PAUSED; in ipc4_be_dai_common_trigger()
739 pipeline->state = SOF_IPC4_PIPE_RESET; in ipc4_be_dai_common_trigger()
746 pipeline->state = SOF_IPC4_PIPE_PAUSED; in ipc4_be_dai_common_trigger()

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