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Searched refs:pipe_dlg_param (Results 1 – 7 of 7) sorted by relevance

/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dml/calcs/
Ddcn_calcs.c445 input->dest.vstartup_start = pipe->pipe_dlg_param.vstartup_start; in pipe_ctx_to_e2e_pipe_params()
446 input->dest.vupdate_offset = pipe->pipe_dlg_param.vupdate_offset; in pipe_ctx_to_e2e_pipe_params()
447 input->dest.vupdate_offset = pipe->pipe_dlg_param.vupdate_offset; in pipe_ctx_to_e2e_pipe_params()
448 input->dest.vupdate_width = pipe->pipe_dlg_param.vupdate_width; in pipe_ctx_to_e2e_pipe_params()
1209 pipe->pipe_dlg_param.vupdate_width = v->v_update_width_pix[input_idx]; in dcn_validate_bandwidth()
1210 pipe->pipe_dlg_param.vupdate_offset = v->v_update_offset_pix[input_idx]; in dcn_validate_bandwidth()
1211 pipe->pipe_dlg_param.vready_offset = v->v_ready_offset_pix[input_idx]; in dcn_validate_bandwidth()
1212 pipe->pipe_dlg_param.vstartup_start = v->v_startup[input_idx]; in dcn_validate_bandwidth()
1214 pipe->pipe_dlg_param.htotal = pipe->stream->timing.h_total; in dcn_validate_bandwidth()
1215 pipe->pipe_dlg_param.vtotal = pipe->stream->timing.v_total; in dcn_validate_bandwidth()
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/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_hwseq.c723 pipe_ctx->pipe_dlg_param.vready_offset, in dcn20_enable_stream_timing()
724 pipe_ctx->pipe_dlg_param.vstartup_start, in dcn20_enable_stream_timing()
725 pipe_ctx->pipe_dlg_param.vupdate_offset, in dcn20_enable_stream_timing()
726 pipe_ctx->pipe_dlg_param.vupdate_width, in dcn20_enable_stream_timing()
1347 if (old_pipe->pipe_dlg_param.vready_offset != new_pipe->pipe_dlg_param.vready_offset in dcn20_detect_pipe_changes()
1348 || old_pipe->pipe_dlg_param.vstartup_start != new_pipe->pipe_dlg_param.vstartup_start in dcn20_detect_pipe_changes()
1349 || old_pipe->pipe_dlg_param.vupdate_offset != new_pipe->pipe_dlg_param.vupdate_offset in dcn20_detect_pipe_changes()
1350 || old_pipe->pipe_dlg_param.vupdate_width != new_pipe->pipe_dlg_param.vupdate_width) in dcn20_detect_pipe_changes()
1475 &pipe_ctx->pipe_dlg_param); in dcn20_update_dchubp_dpp()
1622 int vready_offset = pipe->pipe_dlg_param.vready_offset; in calculate_vready_offset_for_group()
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/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_hw_sequencer.c873 int vready_offset = pipe->pipe_dlg_param.vready_offset; in calculate_vready_offset_for_group()
877 if (other_pipe->pipe_dlg_param.vready_offset > vready_offset) in calculate_vready_offset_for_group()
878 vready_offset = other_pipe->pipe_dlg_param.vready_offset; in calculate_vready_offset_for_group()
881 if (other_pipe->pipe_dlg_param.vready_offset > vready_offset) in calculate_vready_offset_for_group()
882 vready_offset = other_pipe->pipe_dlg_param.vready_offset; in calculate_vready_offset_for_group()
885 if (other_pipe->pipe_dlg_param.vready_offset > vready_offset) in calculate_vready_offset_for_group()
886 vready_offset = other_pipe->pipe_dlg_param.vready_offset; in calculate_vready_offset_for_group()
889 if (other_pipe->pipe_dlg_param.vready_offset > vready_offset) in calculate_vready_offset_for_group()
890 vready_offset = other_pipe->pipe_dlg_param.vready_offset; in calculate_vready_offset_for_group()
940 pipe_ctx->pipe_dlg_param.vstartup_start, in dcn10_enable_stream_timing()
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/linux-6.1.9/drivers/gpu/drm/amd/display/dc/inc/
Dcore_types.h434 struct _vcs_dpi_display_pipe_dest_params_st pipe_dlg_param; member
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/
Ddc_dmub_srv.c545 pipe_data->pipe_config.vblank_data.vstartup_start = vblank_pipe->pipe_dlg_param.vstartup_start; in populate_subvp_cmd_vblank_pipe_info()
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dml/dcn32/
Ddcn32_fpu.c326 pipe->pipe_dlg_param = pipes[pipe_idx].pipe.dest; in dcn32_helper_populate_phantom_dlg_params()
1307 context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest; in dcn32_calculate_dlg_params()
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dml/dcn20/
Ddcn20_fpu.c1058 context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest; in dcn20_calculate_dlg_params()