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Searched refs:pipe_bpp (Results 1 – 25 of 25) sorted by relevance

/linux-6.1.9/drivers/gpu/drm/i915/display/
Dintel_dp.h32 void intel_edp_fixup_vbt_bpp(struct intel_encoder *encoder, int pipe_bpp);
67 void intel_edp_fixup_vbt_bpp(struct intel_encoder *encoder, int pipe_bpp);
Dintel_dp.c679 u32 pipe_bpp) in intel_dp_dsc_get_output_bpp() argument
723 bits_per_pixel = min(bits_per_pixel, pipe_bpp - 1); in intel_dp_dsc_get_output_bpp()
1021 int pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, U8_MAX); in intel_dp_mode_valid() local
1037 pipe_bpp) >> 4; in intel_dp_mode_valid()
1229 bpc = crtc_state->pipe_bpp / 3; in intel_dp_max_bpp()
1354 pipe_config->pipe_bpp = bpp; in intel_dp_compute_link_config_wide()
1476 int pipe_bpp; in intel_dp_dsc_compute_config() local
1485 pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, conn_state->max_requested_bpc); in intel_dp_dsc_compute_config()
1488 pipe_bpp = intel_dp->force_dsc_bpc * 3; in intel_dp_dsc_compute_config()
1489 drm_dbg_kms(&dev_priv->drm, "Input DSC BPP forced to %d", pipe_bpp); in intel_dp_dsc_compute_config()
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Dg4x_hdmi.c42 if (crtc_state->pipe_bpp > 24) in intel_hdmi_prepare()
203 if (pipe_config->pipe_bpp > 24 && in ibx_enable_hdmi()
252 if (pipe_config->pipe_bpp > 24) { in cpt_enable_hdmi()
263 if (pipe_config->pipe_bpp > 24) { in cpt_enable_hdmi()
Dintel_lvds.c292 if (pipe_config->dither && pipe_config->pipe_bpp == 18) in intel_pre_enable_lvds()
435 if (lvds_bpp != pipe_config->pipe_bpp && !pipe_config->bw_constrained) { in intel_lvds_compute_config()
438 pipe_config->pipe_bpp, lvds_bpp); in intel_lvds_compute_config()
439 pipe_config->pipe_bpp = lvds_bpp; in intel_lvds_compute_config()
Dintel_fdi.c254 pipe_config->pipe_bpp); in ilk_fdi_compute_config()
258 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, in ilk_fdi_compute_config()
265 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) { in ilk_fdi_compute_config()
266 pipe_config->pipe_bpp -= 2*3; in ilk_fdi_compute_config()
269 pipe_config->pipe_bpp); in ilk_fdi_compute_config()
Dintel_dp_mst.c78 crtc_state->pipe_bpp = bpp; in intel_dp_mst_compute_link_config()
81 crtc_state->pipe_bpp, in intel_dp_mst_compute_link_config()
97 intel_link_compute_m_n(crtc_state->pipe_bpp, in intel_dp_mst_compute_link_config()
178 limits.max_bpp = min(pipe_config->pipe_bpp, 24); in intel_dp_mst_compute_config()
Dhsw_ips.c194 if (crtc_state->pipe_bpp > 24) in hsw_crtc_state_ips_capable()
Dintel_hdmi.c936 static bool gcp_default_phase_possible(int pipe_bpp, in gcp_default_phase_possible() argument
941 switch (pipe_bpp) { in gcp_default_phase_possible()
1031 if (crtc_state->pipe_bpp > 24) in intel_hdmi_compute_gcp_infoframe()
1035 if (gcp_default_phase_possible(crtc_state->pipe_bpp, in intel_hdmi_compute_gcp_infoframe()
2090 bpc = max(crtc_state->pipe_bpp / 3, 8); in intel_hdmi_compute_bpc()
2138 crtc_state->pipe_bpp = min(crtc_state->pipe_bpp, bpc * 3); in intel_hdmi_compute_clock()
2142 bpc, crtc_state->pipe_bpp); in intel_hdmi_compute_clock()
Dintel_display.c3042 if (crtc_state->dither && crtc_state->pipe_bpp != 30) in i9xx_set_pipeconf()
3046 switch (crtc_state->pipe_bpp) { in i9xx_set_pipeconf()
3049 MISSING_CASE(crtc_state->pipe_bpp); in i9xx_set_pipeconf()
3249 pipe_config->pipe_bpp = 18; in i9xx_get_pipe_config()
3252 pipe_config->pipe_bpp = 24; in i9xx_get_pipe_config()
3255 pipe_config->pipe_bpp = 30; in i9xx_get_pipe_config()
3359 switch (crtc_state->pipe_bpp) { in ilk_set_pipeconf()
3362 MISSING_CASE(crtc_state->pipe_bpp); in ilk_set_pipeconf()
3445 switch (crtc_state->pipe_bpp) { in bdw_set_pipemisc()
3461 MISSING_CASE(crtc_state->pipe_bpp); in bdw_set_pipemisc()
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Dintel_crtc_state_dump.c174 pipe_config->pipe_bpp, pipe_config->dither); in intel_crtc_state_dump()
Dintel_ddi.c353 switch (crtc_state->pipe_bpp) { in intel_ddi_set_dp_msa()
367 MISSING_CASE(crtc_state->pipe_bpp); in intel_ddi_set_dp_msa()
444 switch (crtc_state->pipe_bpp) { in intel_ddi_transcoder_func_reg_val_get()
446 MISSING_CASE(crtc_state->pipe_bpp); in intel_ddi_transcoder_func_reg_val_get()
3311 pipe_config->pipe_bpp = 18; in intel_ddi_read_func_ctl()
3314 pipe_config->pipe_bpp = 24; in intel_ddi_read_func_ctl()
3317 pipe_config->pipe_bpp = 30; in intel_ddi_read_func_ctl()
3320 pipe_config->pipe_bpp = 36; in intel_ddi_read_func_ctl()
3422 intel_edp_fixup_vbt_bpp(encoder, pipe_config->pipe_bpp); in intel_ddi_get_config()
Dintel_crt.c436 if (pipe_config->bw_constrained && pipe_config->pipe_bpp < 24) { in hsw_crt_compute_config()
442 pipe_config->pipe_bpp = 24; in hsw_crt_compute_config()
Dicl_dsi.c1576 pipe_config->pipe_bpp = bdw_get_pipemisc_bpp(crtc); in gen11_dsi_get_config()
1621 if (crtc_state->pipe_bpp < 8 * 3) in gen11_dsi_dsc_compute_config()
1688 pipe_config->pipe_bpp = 24; in gen11_dsi_compute_config()
1690 pipe_config->pipe_bpp = 18; in gen11_dsi_compute_config()
Dvlv_dsi.c299 pipe_config->pipe_bpp = 24; in intel_dsi_compute_config()
301 pipe_config->pipe_bpp = 18; in intel_dsi_compute_config()
1132 pipe_config->pipe_bpp = bdw_get_pipemisc_bpp(crtc); in bxt_dsi_get_pipe_config()
Dintel_panel.c596 if (DISPLAY_VER(dev_priv) < 4 && crtc_state->pipe_bpp == 18) in gmch_panel_fitting()
Dintel_audio.c287 if (crtc_state->pipe_bpp == 36) { in audio_config_hdmi_get_n()
290 } else if (crtc_state->pipe_bpp == 30) { in audio_config_hdmi_get_n()
Dintel_modeset_setup.c134 conn_state->max_bpc = (crtc_state->pipe_bpp ?: 24) / 3; in intel_modeset_update_connector_atomic_state()
Dintel_vdsc.c473 vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3; in intel_dsc_compute_params()
Dintel_display_types.h1127 int pipe_bpp; member
Dintel_display_debugfs.c875 str_yes_no(crtc_state->dither), crtc_state->pipe_bpp); in intel_crtc_info()
2173 seq_printf(m, "Current: %u\n", crtc_state->pipe_bpp / 3); in i915_current_bpc_show()
Dintel_psr.c912 if (crtc_state->pipe_bpp > max_bpp) { in intel_psr2_config_valid()
915 crtc_state->pipe_bpp, max_bpp); in intel_psr2_config_valid()
Dg4x_dp.c399 intel_edp_fixup_vbt_bpp(encoder, pipe_config->pipe_bpp); in intel_dp_get_config()
Dintel_bios.c3447 crtc_state->pipe_bpp = bpc * 3; in fill_dsc()
3449 crtc_state->dsc.compressed_bpp = min(crtc_state->pipe_bpp, in fill_dsc()
Dintel_tv.c1210 pipe_config->pipe_bpp = 8*3; in intel_tv_compute_config()
Dintel_sdvo.c1313 pipe_config->pipe_bpp = 8*3; in intel_sdvo_compute_config()